0. Micro 2012 Lightning Session (PPT)
Onur Mutlu (Carnegie Mellon University)

1. FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory (PDF)
Lei Jiang (University of Pittsburgh)

2. Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access
Niladrish Chatterjee (University of Utah) (PDF)

3. Transactional Memory Architecture and Implementation for IBM System z (PPT)
Christian Jacobi (IBM)

4. Warped-DMR: Light-weight Error Detection for GPGPU (PDF)
Hyeran Jeon (University of Southern California)

5. The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults (PDF)
Damien Hardy (University of Cyprus and University of Rennes 1, IRISA)

6. NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures (PPT)
Andreas Prodromou (University of Cyprus)

7. Cache-Conscious Wavefront Scheduling (PPT)
Timothy G. Rogers (University of British Columbia),

8. Libra: Tailoring SIMD Execution using Heterogeneous Hardware and Dynamic Configurability (PPT)
Yongjun Park (University of Michigan, Ann Arbor)

9. Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor (PDF)
Mark Gebhart (The University of Texas at Austin),

10. Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation (PDF)
Sudhakar Yalamanchili (Georgia Institute of Technology)

11. KnightShift: Scaling the Energy Proportionality Wall Through Server-level Heterogeneity (PDF)
Daniel Wong (University of Southern California)

12. Rethinking DRAM Powermodes for Energy Proportionality (PDF)
Krishna T. Malladi (Stanford University)

13. CoScale: Coordinating CPU and Memory System DVFS in Server Systems (PPT)
Qingyuan Deng (Rutgers University)

14. Predicting Performance Impact of DVFS for Realistic Memory Systems (PDF)
Rustam Miftakhutdinov (The University of Texas at Austin)

15. Vector Extensions for Decision Support DBMS Acceleration (PDF)
Timothy Hayes (Barcelona Supercomputing Center)

16. NOC-Out: Microarchitecting a Scale-Out Processor (PDF)
Pejman Lotfi-Kamran (EPFL)

17. SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads (PPT)
Islam Atta (University of Toronto)

18. Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks (PPT)
Ramon Bertran (Barcelona Supercomputing Center and IBM Research),

19. AUDIT: Stress Testing the Automatic Way (PDF)
Youngtaek Kim (The University of Texas at Austin)

20. Accurate Fine-Grained Processor Power Proxies (PDF)
Wei Huang (AMD)

21. Fundamental Latency Trade-offs in Architecting DRAM Caches (PDF)
Moinuddin Qureshi (Georgia Institute of Technology)

22. A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch (PPT)
Jaewoong Sim (Georgia Institute of Technology)

23. CoLT: Coalesced Large-Reach TLBs (PPT)
Binh Pham (Rutgers University)

24. NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers (PDF)
Lizhong Chen (University of Southern California)

25. Dynamic Reconfiguration of 3D Photonic On-chip Interconnects for Maximizing Performance and Improving Fault Tolerance (PPT)
Randy Morris (University of Arizona/NSF)

26. Addressing End-to-End Memory Access Latency in NoC-Based Multicores (PDF)
Emre Kultursay, Mahmut Kandemir (The Pennsylvania State University)

27. MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP (PPT)
Khubaib (UT Austin)

28. Composite Cores: Pushing Heterogeneity into a Core (PPT)
Andrew Lukefahr (University of Michigan)

29. Control-Flow Decoupling (PDF)
Rami Sheikh (North Carolina State University)

30. Spatiotemporal Coherence Tracking (PDF)
Mohammad Alisafaee (EPFL)

31. Predicting Coherence Communication by Tracking Synchronization Points at Run Time (PPT)
Socrates Demetriades (University of Pittsburgh)

32. Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically (PDF)
Josep Torrellas (University of Illinois at Urbana-Champaign)

33. Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy (PPT)
Snehasish Kumar (Simon Fraser University)

34. Improving Cache Management Policies Using Dynamic Reuse Distances (PPT)
Nam Duong (UC Irvine)

35. Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem (PDF)
Petar Radojkovic (Barcelona Supercomputing Center)

36. Inferred Models for Dynamic and Sparse Hardware-Software Spaces (PPT)
Weidan Wu (Duke University)

37. SMARTQ: Software-Managed Alias Register Queue for Dynamic Optimizations (PPT)
Cheng Wang (Intel Labs)

38. Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization (PDF)
Alain Ketterlin (INRIA & Université de Strasbourg)

39. Neural Acceleration for General-Purpose Approximate Programs (PDF)
Adrian Sampson (University of Washington)

40. Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator (PDF)
Jan van Lunteren (IBM Research)