18:00 - 21:00 Welcome ReceptionRoom: Dining Hall

07:30 - 17:00 Registration Room: Auditorium Foyer

08:00 - 08:30 CoffeeRoom: Dining Hall

08:30 - 09:00 Welcome Message from General & Program Chairs Rooms: Main Auditorium & Umney Theatre

General Chair: Krisztian Flautner

Program Co-chairs: Emre Ozer & Thomas Wenisch

09:00 - 10:00 Keynote I Rooms: Main Auditorium & Umney Theatre

Keynote Title: From IoT to Services - Efficiency Matters

Keynote Speaker: Mike Muller, CTO, ARM

Session Chair: Thomas Wenisch

10:00 - 10:25 Coffee BreakRoom: Dining Hall

10:25 - 12:25 Lightning Session Rooms: Main Auditorium & Umney Theatre

Session Chair: Thomas Conte

12:25 - 13:25 LunchGarden Restaurant/Dining Hall

13:25 - 15:30 Session 1A: Stacked DRAM Room: Umney Theatre & Lounge

Session Chair: Thomas Pawlowski

CAMEO:A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache

Chiachen Chou (Georgia Tech.), Aamer Jaleel (Intel), Moinuddin K. Qureshi (Georgia Tech.)

Transparent Hardware Management of Stacked DRAM as Part of Memory

Jaewoong Sim (Georgia Tech.), Alaa R. Alameldeen (Intel), Zeshan Chishti (Intel), Chris Wilkerson (Intel), Hyesoon Kim (Georgia Tech.)

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

Djordje Jevdjic (EPFL), Gabriel Loh (AMD), Cansu Kaynak (EPFL), Babak Falsafi (EPFL)

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth

Nagendra Gulur (Texas Instruments), Govindarajan R. (Indian Institute of Science), Raman Manikantan (Indian Institute of Science), Mahesh Mehendale (Texas Instruments)

Citadel: Efficiently Protecting Stacked Memory From Large Granularity Failures

Prashant J. Nair (Georgia Tech.), David A. Roberts (AMD), Moinuddin K. Qureshi (Georgia Tech.)

13:25 - 15:30 Session 1B: GPGPU and Data Parallel Architectures Room: Main Auditorium

Session Chair: Natalie Enright Jerger

Locality-Aware Mapping of Nested Parallel Patterns on GPUs

HyoukJoong Lee (Stanford Uni.), Kevin J. Brown (Stanford Uni.), Arvind K. Sujeeth (Stanford Uni.), Tiark Rompf (EPFL, Oracle), Kunle Olukotun (Stanford Uni.)

Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists

Ji Kim (Cornell Uni.), Christopher Batten (Cornell Uni.)

PORPLE: An Extensible Optimizer for Portable Data Placement on GPU

Guoyang Chen (The College of William and Mary), Bo Wu (Colorado School of Mines), Dong Li (Oak Ridge National Laboratory), Xipeng Shen (The College of William and Mary)

Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures

Yunsup Lee (University of California, Berkeley), Mark Stephenson (NVIDIA), Vinod Grover (NVIDIA), Ronny Krashinsky (NVIDIA), Stephen W. Keckler (NVIDIA and the University of Texas at Austin), Krste Asanovic (University of California, Berkeley)

Managing GPU Concurrency in Heterogeneous Architectures

Onur Kayiran (Penn State), Nachiappan Chidambaram Nachiappan (Penn State), Adwait Jog (Penn State), Rachata Ausavarungnirun (Carnegie Mellon University), Mahmut T. Kandemir (Penn State), Gabriel H. Loh (AMD), Onur Mutlu (Carnegie Mellon University), Chita R. Das (Penn State)

15:30 - 15:55 Coffee BreakRoom: Dining Hall

15:55 - 18:00 Session 2A: Memory Systems, Scheduling and Optimization Room: Main Auditorium

Session Chair: Gabe Loh

Load Value Approximation

Joshua San Miguel (University of Toronto), Mario Badr (University of Toronto), Natalie Enright Jerger (University of Toronto)

Arbitrary Modulus Indexing

Jeffrey R. Diamond (University of Texas at Austin), Donald S. Fussell (University of Texas at Austin), Stephen W. Keckler (NVIDIA and University of Texas at Austin)

FIRM: Fair and High-performance Memory Control for Persistent Memory Systems

Jishen Zhao (Pennsylvania State University/HP Labs/Carnegie Mellon University), Onur Mutlu (Carnegie Mellon University), Yuan Xie (University of California, Santa Barbara/Pennsylvania State University)

Short-Circuiting Memory Traffic in Handheld Platforms

Praveen Yedlapalli (Penn State), Nachiappan Chidambaram Nachiappan (Penn State), Niranjan Soundararajan (Intel ), Anand Sivasubramaniam (Penn State), Mahmut Kandemir (Penn State), Chita R. Das (Penn State)

Efficient Memory Virtualization

Jayneel Gandhi (University of Wisconsin - Madison), Arkaprava Basu (AMD), Michael M. Swift (University of Wisconsin - Madison), Mark D. Hill (University of Wisconsin - Madison)

15:55 - 18:00 Session 2B: Security Room: Umney Theatre & Lounge

Session Chair: Ben Serebrin

Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution

Dmitry Evtyushkin (SUNY Binghamton), Jesse Elwell (SUNY Binghamton), Meltem Ozsoy (SUNY Binghamton), Dmitry Ponomarev (SUNY Binghamton), Nael Abu-Ghazaleh (SUNY Binghamton), Ryan Riley (Qatar Uni.)

Random Fill Cache Architecture

Fangfei Liu (Princeton Uni.), Ruby B. Lee (Princeton Uni.)

CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware

Jie Chen (George Washington Uni.), Guru Venkataramani (George Washington Uni.)

Continuous, Low Overhead, Run-Time Validation of Program Executions

Erdem Aktas (SUNY Binghamton), Furat Afram (SUNY Binghamton), Kanad Ghose (SUNY Binghamton)

A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events

Robert Callan (Georgia Tech), Alenka Zajic (Georgia Tech), Milos Prvulovic (Georgia Tech)

19:00 - 22:00 MICRO Business Meeting Room: Dining Hall

07:30 - 17:00 Registration Room: Auditorium Foyer

07:30 - 08:00 CoffeeRoom: Dining Hall

08:00 - 09:00 Keynote II Rooms: Main Auditorium & Umney Theatre

Keynote Title: The End of Moore's Law - Again

Keynote Speaker: Trevor Mudge, University of Michigan

Session Chair: Emre Ozer

09:00 - 09:15 Coffee BreakRoom: Dining Hall

09:15 - 10:30 Session 3A: Methodology, Modeling and Tools Room: Main Auditorium

Session Chair: Reetu Das

RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks

Jaewon Lee (POSTECH), Hanhwi Jang (POSTECH), Jangwoo Kim (POSTECH)

GPUMech: GPU Performance Modeling Technique based on Interval Analysis

Jen-Cheng Huang (Georgia Tech.), Joo Hwan Lee (Georgia Tech.) , Hyesoon Kim (Georgia Tech.) , Hsien-Hsin S. Lee (Georgia Tech.)

PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research

Derek Lockhart (Cornell Uni.), Gary Zibrat (Cornell Uni.) , Christopher Batten (Cornell Uni.)

09:15 - 10:30 Session 3B: Reliability and Fault Tolerance Room: Umney Theatre & Lounge

Session Chair: Avi Mendelson

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Mark Wilkening (AMD, Northeastern Uni.), Vilas Sridharan (AMD), David Kaeli (Northeastern Uni.), Sudhanva Gurumurthi (AMD), Fritz Previlon (Northeastern Uni.), Si Li (AMD)

Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors

Anys Bacha (Ohio State), Radu Teodorescu (Ohio State)

Harnessing Soft Computations for Low-budget Fault Tolerance

Daya S. Khudia (University of Michigan), Scott Mahlke (University of Michigan)

10:30 - 10:45 Coffee Break Room: Dining Hall

10:45 - 12:00 Session 4A: TLB and Cache Optimization Room: Main Auditorium

Session Chair: Boris Grot

Skewed Compressed Cache

Somayeh Sardashti (University of Wisconsin - Madison), Andre Seznec (INRIA), David Wood (University of Wisconsin - Madison)

Adaptive Cache Management for Energy-efficient GPU Computing

Xuhao Chen (National University of Defense Technology), Li-Wen Chang (University of Illinois at Urbana-Champaign), Christopher I. Rodrigues (University of Illinois at Urbana-Champaign), Lv Jie (University of Illinois at Urbana-Champaign), Zhiying Wang (National University of Defense Technology), Wen-mei Hwu (University of Illinois at Urbana-Champaign)

Futility Scaling: High-Associativity Cache Partitioning

Ruisheng Wang (University of Southern California), Lizhong Chen (University of Southern California)

10:45 - 12:00 Session 4B: Managing Voltage and Time Room: Umney Theatre & Lounge

Session Chair: Vijay Reddi

Voltage Noise in Multi-core Processors: Empirical Characterization and Optimization Opportunities

Ramon Bertran (IBM Research), Alper Buyuktosunoglu (IBM Research), Pradip Bose (IBM Research), Timothy J. Slegel (IBM Systems and Technology Group), Gerard Salem (IBM Systems and Technology Group), Sean Carey (IBM Systems and Technology Group), Richard F. Rizzolo (IBM Systems and Technology Group), Thomas Strach (IBM Systems and Technology Group)

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks

Waclaw Godycki (Cornell Uni.), Christopher Torng (Cornell Uni.), Ivan Bukreyev (Cornell Uni.), Alyssa Apsel (Cornell Uni.), Christopher Batten (Cornell Uni.)

Micro-sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated Systems

Jeongseob Ahn (KAIST), Chang Hyun Park (KAIST), Jaehyuk Huh (KAIST)

12:00 - 13:20 Lunch & Poster Session Room: Dining Hall

13:30 - 16:00 Guided Cambridge Tour and Punting

16:15 - 16:30 Arrival at Cambridge Union Debating Chamber (View Map)

16:30 - 17:30 Bob Rau Award PresentationPlace: Cambridge Union Debating Chamber

Recipient: Wen-mei Hwu (University of Illinois, Urbana-Champaign) (View Video) Bob Rau Award Talk presentation

17:30 - 18:00 DrinksPlace: Cambridge Union Debating Chamber

18:00 - 19:15 Hot-DebatePlace: Cambridge Union Debating Chamber

Moderator: Trevor Mudge

Debate Topic: It is the End of the Road for the von Neumann Architecture (View Video)

19:30 - 21:30 DinnerPlace: Kings College (View Map)

07:30 - 17:00 Registration Room: Auditorium Foyer

08:00 - 08:30 CoffeeRoom: Dining Hall

08:30 - 09:30 Keynote III Rooms: Main Auditorium & Umney Theatre

Keynote Title: Investigating the Brain's Computational Paradigm - Presentation

Keynote Speaker: James E. Smith, University of Wisconsin - Madison

Session Chair: David Wood

09:30 - 09:50 Coffee BreakRoom: Dining Hall

09:50 - 11:30 Session 5A: Energy-efficient Computation Room: Main Auditorium

Session Chair: Drew Hilton

SMiTe: Precise QoS Prediction on Real System SMT Processors to Improve Utilization in Warehouse Scale Computers

Yunqi Zhang (University of Michigan), Michael A. Laurenzano (University of Michigan), Jason Mars (University of Michigan), Lingjia Tang (University of Michigan)

A Front-end Execution Architecture for High Energy Efficiency

Ryota Shioya (Nagoya University) , Masahiro Goshima (National Institute of Informatics), Hideki Ando (Nagoya University)

Execution Drafting: Energy Efficiency Through Computation Deduplication

Michael McKeown (Princeton Uni.), Jonathan Balkind (Princeton Uni.), David Wentzlaff (Princeton Uni.)

PPEP: Online Performance, Power and Energy Prediction Framework and DVFS Space Exploration

Bo Su (NUDT), Junli Gu (AMD), Li Shen (NUDT), Wei Huang (AMD), Joseph Greathouse (AMD), ZhiYing Wang (NUDT)

09:50 - 11:30 Session 5B: Interconnects Room: Umney Theatre & Lounge

Session Chair: Jangwoo Kim

NoC Architectures for Silicon Interposer Systems

Ajaykumar Kannan (University of Toronto), Zimo Li (University of Toronto), Natalie Enright Jerger (University of Toronto), Gabriel H. Loh (AMD)

Hi-Rise: A High-Radix Switch for 3D Integration with Single-cycle Arbitration

Supreet Jeloka (University of Michigan), Reetuparna Das (University of Michigan), Ronald G. Dreslinski (University of Michigan), Trevor Mudge (University of Michigan), David Blaauw (University of Michigan)

Multi-GPU System Design with Memory Networks

Gwangsun Kim (KAIST), Minseok Lee (KAIST), Jiyun Jeong (KAIST), John Kim (KAIST)

Dodec: Random-Link, Low-Radix On-Chip Networks

Haofan Yang (University of Toronto), Jyoti Tripathi (University of Toronto), Natalie Enright Jerger (University of Toronto), Dan Gibson (Google)

11:30 - 12:00 Test-of-Time Awards Rooms: Main Auditorium & Umney Theatre

Chair: Rich Belgard

12:00 - 13:00 LunchGarden Restaurant/Dining Hall

13:00 - 14:40 Session 6A: Branch Prediction and Prefetching Room: Main Auditorium

Session Chair: Mike Ferdman

Wormhole: Wisely Predicting Multidimensional Branches

Jorge Albericio (University of Toronto), Joshua San Miguel (University of Toronto), Natalie Enright Jerger (University of Toronto), Andreas Moshovos (University of Toronto)

Bias-Free Branch Predictor

Dibakar Gope (University of Wisconsin-Madison), Mikko H. Lipasti (University of Wisconsin-Madison)

Loop-Aware Memory Prefetching Using Code Block Working Sets

Adi Fuchs (Technion), Shie Mannor (Technion), Uri Weiser (Technion), Yoav Etsion (Technion)

BuMP: Bulk Memory Access Prediction and Streaming

Stavros Volos (EPFL), Javier Picorel (EPFL), Boris Grot (University of Edinburgh), Babak Falsafi (EPFL)

13:00 - 14:40 Session 6B: Compilation and Code Generation Room: Umney Theatre & Lounge

Session Chair: Luis Ceze

Protean Code: Achieving Near-free Online Code Transformations for Warehouse Scale Computers

Michael A. Laurenzano (University of Michigan), Yunqi Zhang (University of Michigan), Lingjia Tang (University of Michigan), Jason Mars (University of Michigan)

Compiler Support for Optimizing Memory Bank-Level Parallelism

Wei Ding (Penn State), Diana Guttman (Penn State), Mahmut Kandemir (Penn State)

Architectural Specialization for Inter-Iteration Loop Dependence Patterns

Shreesha Srinath (Cornell Uni.), Berkin Ilbeyi (Cornell Uni.), Mingxing Tan (Cornell Uni.), Gai Liu (Cornell Uni.), Zhiru Zhang (Cornell Uni.), Christopher Batten (Cornell Uni.)

Specializing Compiler Optimizations Through Programmable Composition For Dense Matrix Computations

Qing Yi (University of Colorado at Colorado Springs), Qian Wang (Institute of Software, Chinese Academy of Sciences), Huimin Cui (Institute of Software, Chinese Academy of Sciences)

14:40 - 15:10 Coffee Break Room: Dining Hall

15:10 - 17:15 Session 7: Best Paper Nominees Rooms: Main Auditorium & Umney Theatre

Session Chair: Ron Dreslinski

Best Paper - DaDianNao: A Machine-Learning Supercomputer

Yunji Chen (ICT), Tao Luo (ICT), Shaoli Liu (ICT), Shijin Zhang (ICT), Liqiang He (INRIA), Jia Wang (ICT), Ling Li (ICT), Tianshi Chen (ICT), Zhiwei Xu (ICT), Ninghui Sun (ICT), Olivier Temam (INRIA)

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

David Kadjo (Texas A&M Uni.), Jinchun Kim (Texas A&M Uni.), Prabal Sharma (Samsung Austin R&D), Reena Panda (UT Austin), Paul Gratz (Texas A&M Uni.), Daniel Jimenez (Texas A&M Uni.)

PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models

Daniel Lustig (Princeton Uni.), Michael Pellauer (Intel), Margaret Martonosi (Princeton Uni.)

Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution

Ankit Sethia (University of Michigan), Scott Mahlke (University of Michigan)

COMP: Compiler Optimizations for Manycore Processors

Linhai Song (University of Wisconsin-Madison), Min Feng (NEC Laboratories America), Nishkam Ravi (Cloudera), Yi Yang (NEC Laboratories America), Srimat Chakradhar (NEC Laboratories America)

17:15 - 17:45 Best Paper Award Rooms: Main Auditorium & Umney Theatre

17:45 - 18:00 Closing Remarks