The 41st Annual IEEE/ACM International Symposium on Microarchitecture, 2008

SCHEDULE

	Saturday, Nov. 8
	Villa Monastero	Villa Olmo	Villa Sucota	Villa Giulia	Villa Melzi
Morning Session 8:30-10:00 coffe break 10:30-12:00	W2	W4	T2	T4
Afternoon Session 13:30-15:00 coffe break 15:30-17:00	W5	W3	T2	T7	T9
	Sunday, Nov. 9
	Villa Monastero	Villa Olmo	Villa Sucota	Villa Giulia	Villa Melzi
Morning Session 8:30-10:00 coffe break 10:30-12:00	W1	T1	T3	T11	T6
Afternoon Session 13:30-15:00 coffe break 15:30-17:00	W1	T10	T3	T8	T5

WORKSHOPS

W1. dasCMP: Workshop on Design, Architecture and Simulation of Chip Multi-Processors
Organizers: Norman Jouppi, Rakesh Kumar, and Dean Tullsen HP Labs, University of Illinois at Urbana-Champaign and University of California at San Diego

W2. Streaming Systems: From Web and Enterprise to Multicore
Organizers: Rodric Rabbah, Xiaowei Shen, and Saman Amarasinghe, IBM and Massachusetts Institute of Technology

W3. New Frontiers in High-performance and Hardware-aware Computing (HipHac)
Organizers: Rainer Buchty and Jan-Philipp Weiß, Karlsruhe Institute of Technology (KIT)

W4. 3rd Workshop on Dependable Architecture (WDA-3)
Organizers: Yiannakis Sazeides, Osman S. Unsal, and Oguz Ergin, University of Cyprus, Barcelona Supercomputing Center, and TOBB University

W5. Network on Chip Architectures (NoCArc)
Organizers: Maurizio Palesi and Shashi Kumar, University of Catania, Italy and Jonkoping University

TUTORIALS

T1. Programming Throughput-Oriented Architectures with Ct
Organizers: Anwar Ghuloum, Gansha Wu and Xin Zhou, Intel

T2. On-Chip Communication Architectures: Busses, Networks-on-Chip and Beyond
Organizers: Nikil Dutt, Luca Benini, and Sudeep Pasricha, University of California at Irvine and University of Bologna

T3. Coherence and Memory Consistency Models
Organizer: Michel Dubois, University of Southern California

T4. VLIW Compilation Environment and Multi-Processor Architecture of Diopsis, the RISC + floating-Point VLIW DSP System-On-Chip Designed for High Quality Acoustic Applications
Organizers: Gert Goossens, Pier Stanislao Paolucci and Piergiovanni Bazzana, ATMEL Roma and TARGET Compiler Technologies

T5. COTSon: Infrastructure for System-Level Simulation
Organizers: Theresa Frawley, Vincent Lim, Ayose Falcon, Paolo Faraboschi and Daniel Ortega, HP Labs and AMD

T6. Design Variability: Trends, Models, and Design Solutions
Organizers: Keith Bowman, David Brooks, Gu-Yeon Wei and Chris Wilkerson, Intel and Harvard

T7. Performance Tools for Understanding the Behavior of Running Programs on the Cell B.E
Organizers: Bilha Mendelson, Gadi Haber and Thomas Chen, IBM

T8. Modeling, Verification and Mapping of Applications on WSN Architectures
Organizers: Franco Fummi, Andrea Acquaviva, Davide Quaglia and Giovanni Perbellini, University of Verona and EDALab

T9. Microprocessor Memory Array Circuits for Architects
Organizers: Shih-Lien Lu, Dinesh Somasekhar and Steven Hsu, Intel

T10. Changing Factors in Memory System Design
Organizers: Kenneth Wright and Hillery Hunter, IBM

T11. CAD Solutions for System-Level Power Optimization
Organizers: Enrico Macii and Massimo Poncino, Politecnico di Torino, Italy