Tutorial T11
CAD
Solutions for System-Level Power Optimization
Abstract
In the last decade, power and energy have become primary
design metrics not just for energy-constrained applications but also for
generic architectures, as a limiting factor preventing aggressive performance
optimizations. Moreover, with the advent of sub-100nm technologies, static power
consumption due to leakage currents has become an additional factor, further
complicating the picture and making total
power optimization a must.
The objective of this tutorial is to
provide a comprehensive review of architectural dynamic and static power reduction
techniques in the sub-100nm regime, and their implications on the design
automation side.
The tutorial is structured in three major parts.
The first part provides an overview of
technology and scaling trends that have
caused an increase of non-idealities in the deca-nanometer
era; Issues like device physics that leads to sub-threshold and gate leakage, wire
geometries that favor parasitic effects, temperature-induced and
process-induced variations will be discussed along with their effect on circuit
design variables.
The second part of the tutorial will
discuss architectural techniques for dynamic and static power reduction;
this will include techniques such as low-power interconnects, power management,
power gating, energy-aware cache/memory design and
architectures.
The third part provides a brief survey
of the solutions available from the EDA market; this part will also serve as an
EDA perspective of the previously discussed design solutions, in order to
emphasize the challenges involved in their automation.
The tutorial is intended for designers
and CAD engineers involved in power-efficient architectures, design techniques
and methodologies for next generation technologies. A basic background of VLSI
design and CAD is useful though not strictly required.
Contents
Part I: Technology Trends
·
Static
and dynamic power
·
Impact
of temperature
·
Process
variations
Part II: Dynamic and static architectural
power optimization
·
Dynamic
power/energy optimizations:
o
Hardware/software
partitioning
o
Choice
of data representation
o
Low-energy
Bus encoding
o
Memory
Memory hierarchy design
o
Memory
code and data compression
o
Dynamic
power management
o
Battery modeling and battery-driven power management
·
Static
power/energy optimizations:
o
Power
gating
o
Use
of multiple threshold voltages
o
VT
modulation by adaptive body-bias
o
Leakage-aware
Memory architectures
Part III: Survey of academic and
commercial CAD solutions
Expected duration:
The tutorial is
structured as a half-day course.
Speakers
Prof. Enrico Macii
|
Politecnico di Torino, ITALY
|
Prof. Massimo Poncino
|
Politecnico di Torino, ITALY
|
Enrico Macii
Enrico Macii is a Full Professor of
Electrical and Computer Engineering at Politecnico di Torino.
His research interests include several aspects of the
computer-aided design of digital integrated circuits and systems, with
particular emphasis on methodologies, algorithms and tools for power estimation
and optimization of
systems described at various levels of the design hierarchy.
He has authored over 300 scientific publications. Enrico Macii is the Editor-in-Chief of the IEEE
Transactions on Computer-Aided Design of Integrated Circuits and
Systems. Prior to that, he was an Associate Editor for the same journal
(1997-2005) and an Associate Editor of the ACM Transactions on Design
Automation of Electronic Systems (2000-2005). He was the Guest Editor of several Special Issues
on power-related topics on various IEEE journals and magazines.
He has served the as General Chair, Program Chair, and on the
Technical Program Committee of several IEEE and ACM conferences and workshops,
including DAC, DATE, ISLPED, GLSVLSI and PATMOS.
Enrico Macii is a Fellow of the IEEE, and a
Member of the Advisory Committee of the IEEE Council on Electronic Design
Automation (CEDA).
Massimo Poncino
Massimo Poncino is a Full Professor
of Electrical and Computer Engineering at Politecnico di Torino.
He received a Dr.Eng. degree
in Electrical Engineering and the Ph.D. degree in Computer Engineering, both
from Politecnico di Torino.
His research interests include several aspects of design
automation of digital systems, with particular emphasis on the modeling and
optimization of low-power systems at different levels of abstractions.
He has co-authored over 200 journal and conference papers, as well
as a book on low-power memory design.
Massimo Poncino is an Associate Editor of the IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, and he serves on the
Technical Program Committee of several IEEE and ACM design
automation conferences and workshops, including,
DATE, ISLPED, GLSVLSI and PATMOS.
Prof. Poncino is a Member of the ACM SIGDA Low-Power Technical Committee.