Tutorial, MICRO 2008

Sunday Afternoon Session

Changing Factors in Memory System Design

Organizers

Kenneth Wright, IBM Server & Technology Group, Austin, TX

Hillery Hunter, IBM Research, Yorktown Heights, NY

Abstract

In recent years, architects have debated whether the “memory wall” should be scaled by improving (a) latency or (b) bandwidth. DDR standards have dictated successively increasing DRAM frequencies, and systems have been built with increasing numbers of memory channels and sockets. However, just as power (and accordingly, frequency) limitations have arisen in processor design, new challenges are emerging at all levels of the memory system – from the processor’s perspective (the way data is accessed and the complexity of the memory controller) to the manufacturer’s perspective (the way DRAM chips are architected, what power management modes are provided, etc.).

For DRAMs, lower frequencies, a lag in lithography generations, and specialized silicon processing have somewhat hidden the power wall. In this tutorial, we will show that the "memory wall" architects so frequently discuss is no longer a latency wall or a bandwidth wall, but rather an emerging power wall. We will start with the basics of DRAM, DIMM, and memory controller design, and then explore the challenges of memory subsystem power delivery, power consumption, and cooling. Tutorial material will be based on extensive measurements of real DIMMs and system hardware, providing a unique look at discontinuities in memory system behavior and the particular challenges of server-class systems. The tutorial will be interactive, and will include a hands-on exercise in balanced processor/memory design for multiple compute classes (embedded to server and HPC).

Topics to be covered

· DRAM architecture and design fundamentals

· Memory DIMM design fundamentals

· Memory controller design fundamentals

· Fundamentals of memory power consumption

· Memory power management modes

· Discontinuities in memory performance and power

· System-level factors in memory design (space, cooling, etc.)

· System-level energy management

Expected duration

4 Hours

Organizer Biographies

Kenneth Wright is a Senior Engineer in the IBM Server & Technology Group, Austin, TX. He is presently the End-to-End Memory Sub-system lead for ipServer Development, and was previously Development Bring-up Lead for Power4+ and Power5+ processor systems. He received his MS in Electrical Engineering from the University of Virginia, where he worked on the Stream Memory Controller (with the group that published the original “memory wall” paper), and his BS in Computer Engineering and BS in Electrical Engineering from North Carolina State University.

Hillery Hunter is a Research Staff Member in the Exploratory Systems Architecture Department of IBM's T.J. Watson Research Center in Yorktown Heights, NY. She is interested in cross-disciplinary research, spanning circuits, microarchitecture, and compilers to achieve new solutions to traditional problems. She has published in the area of embedded DRAM, and is currently engaged with IBM server development as DDR3-generation end-to-end memory power lead. She received the Ph.D. degree in Electrical Engineering from the University of Illinois, Urbana-Champaign.