"Future Architectures will Incorporate HPUs" Details

Session Chair: Doug Carmean

Active Management of Timing Guardband to Save Energy in POWER7

Charles Lefurgy, Alan Drake, Michael Floyd, Malcolm Allen-Ware, Bishop Brock, Jose Tierno, and John Carter (IBM)

 

Bundled Execution of Recurring Traces for Energy-Efficient General Purpose Processing

Shantanu Gupta, Shuguang Feng, Amin Ansari, and Scott Mahlke (University of Michigan Ann Arbor) and David August (Princeton University)

 

Minimalist Open-page: A DRAM Page-mode Scheduling Policy for the Many-core Era

Dimitris Kaseridis (The University of Texas at Austin), Jeff Stuecheli (IBM), and Lizy K. John (The University of Texas at Austin)

Session Chair: Uri Weiser

The NoX Router

Mitchell Hayenga and Mikko Lipasti (University of Wisconsin-Madison)

 

A Systematic Methodology to Develop Resilient Cache Coherence Protocols

Konstantinos Aisopos (Princeton University) and Li-Shiuan Peh (MIT)

Dataflow Execution of Sequential Imperative Programs on Multicore Architectures

Gagan Gupta and Guri Sohi (University of Wisconsin-Madison)

Session Chair: Chita Das

Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication

Tushar Krishna and Li-Shiuan Peh (MIT) and Bradford M. Beckmann and Steven K. Reinhardt (AMD)

Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks

George Michelogiannakis, Nan Jiang, Daniel Becker, and William J.Dally (Stanford University)

Resilient Microring Resonator Based Photonic Networks

Christopher Nitta, Matthew Farrens, and Venkatesh Akella (University of California, Davis)

FeatherWeight: Low-cost Optical Arbitration with QoS Support

Yan Pan (Globalfoundries Inc.), John Kim (KAIST), and Gokhan Memik (Northwestern University)

Session Chair: Miko Lipasti

A new case for the TAGE branch predictor

Andre Seznec (INRIA/IRISA)

Identifying Critical Instructions to Boost Timing Speculation

Jing Xin and Russ Joseph (Northwestern University)

Idempotent Processor Architecture

Marc de Kruijf and Karthikeyan Sankaralingam (University of Wisconsin - Madison)

Proactive Instruction Fetch

Michael Ferdman (CMU /EPFL) and Cansu Kaynak and Babak Falsafi (EPFL)

Session Chair: Babak Falsafi

QsCores: Configurable Co-processors to Trade Dark Silicon for Energy Efficiency in a Scalable Manner

Ganesh Venkatesh, John Sampson, Nathan Goulding, Sravanthi K V, Steven Swanson, and Michael Taylor (UCSD)

Pack & Cap: Adaptive DVFS and Thread Packing Under Power Caps

Ryan Cochran (Brown University), Can Hankendi and Ayse K. Coskun (Boston University), and Sherief Reda (Brown University)

Preventing PCM Banks from Seizing Too Much Power

Andrew Hay (University of Auckland), Karin Strauss (Microsoft Research), Tim Sherwood (UC Santa Barbara), Gabriel Loh (AMD Research), and Doug Burger (Microsoft Research)

CRAM: Coded Registers for Amplified Multiporting

Vignyan Reddy Kothinti Naresh, David J. Palframan, and Mikko H. Lipasti (University of Wisconsin-Madison)

Session Chair: Luis Ceze

ATDetector: Improving the Accuracy of a Commercial Data Race Detector by Identifying Address Transfer

Jiaqi Zhang (University of California San Diego), Weiwei Xiong (University of Illinois Urbana Champaign), Yang Liu, Soyeon Park, and Yuanyuan Zhou (University of California San Diego), and Zhiqiang Ma (Intel)

CoreRacer: A Practical Memory Race Recorder for Multicore x86 TSO Processors

Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Gottschlich, Jungwoo Ha, and Youfeng Wu (Intel)

Manager-Client Pairing: A Framework for Implementing Coherence Hierarchies

Jesse G. Beu, Michael C. Rosier, and Thomas M. Conte (Georgia Institute of Technology)

TransCom: Transforming Stream Communication for Load Balance and Efficiency in Networks-on-Chip

Ahmed H. Abdel-Gawad and Mithuna Thottethodi (Purdue University)

"Life After Dennard and How I Learned to Love the Picojoule"  Details

Session Chair: Karin Strauss

Bubble-Up: Increasing Sensible Co-locations for Improved Utilization in Modern Warehouse Scale Computers

Jason Mars and Lingjia Tang (University of Virginia), Robert Hundt (Google), and Kevin Skadron and Mary Lou Soffa (University of Virginia)

System-Level Integrated Server Architectures for Scale-Out Datacenters

Sheng Li, Kevin Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, and Norm Jouppi (HP Labs)

Architectural Support for Secure Virtualization under a Vulnerable Hypervisor

Seongwook jin, Jeongseob Ahn, Sanghoon Cha, and Jaehyuk Huh (KAIST)

Session Chair: Paolo Faraboschi

Complementing User-Level Coarse-Grain Parallelism with Implicit Speculative Parallelism

Nikolas Ioannou and Marcelo Cintra (University of Edinburgh)

Hardware Transactional Memory for GPU Architectures

Wilson Wai Lun Fung and Inderpreet Singh (University of British Columbia), Andrew Brownsword (unaffiliated), and Tor M. Aamodt (University of British Columbia)

Improving GPU Performance via Large Warps and Two-Level Warp Scheduling

Veynu Narasiman (The University of Texas at Austin), Chang Joo Lee (Intel Corporation), Michael Shebanow (NVIDIA Corporation), Rustam Miftakhutdinov (The University of Texas at Austin), Onur Mutlu (Carnegie Mellon University), and Yale N. Patt (The University of Texas at Austin)

Session Chair: Gabriel Loh

Pay-As-You-Go: Low-Overhead Hard-Error Correction for Phase Change Memories

Moinuddin Qureshi (IBM)

Multi Retention Level STT-RAM Cache Designs with a Dynamic Refresh Scheme

Zhenyu Sun, Xiuyuan Bi, and Hai Li (Polytechnic Institute of New York University), Weng-Fai Wong and Zhong-liang Ong (National University of Singapore), and Xiaochun Zhu and Wenqing Wu (Qualcomm)

A Resistive TCAM Accelerator for Data-Intensive Computing

Qing Guo, Xiaochen Guo, Yuxin Bai, and Engin Ipek (University of Rochester)

Session Chair: Jaleel Aamer

A Register-file Approach for Row Buffer Caches in Die-stacked DRAMs

Gabriel H. Loh (AMD)

Parallel Application Memory Scheduling

Eiman Ebrahimi and Rustam Miftakhutdinov (The University of Texas at Austin), Chang Joo Lee (Intel Corporation), Jose Joao (The University of Texas at Austin), Onur Mutlu and Chris Fallin (Carnegie Mellon University), and Yale N. Patt (The University of Texas at Austin)

Reducing Memory Interference in Multi-Core Systems via Application-Aware Memory Channel Partitioning

Sai Prashanth Muralidhara (Pennsylvania State University), Lavanya Subramanian and Onur Mutlu (Carnegie Mellon University), Mahmut Kandemir (Pennsylvania State University), and Thomas Moscibroda (Microsoft Research)

Session Chair: Ed Suh

Accelerating Microprocessor Silicon Validation by Exposing ISA Diversity

Nikos Foutris and Dimitris Gizopoulos (University of Athens), Mihalis Psarakis (University of Piraeus), and Xavier Vera and Antonio Gonzalez (Intel Barcelona Research Center)

 
Low-cost, Fine-grained Transient Fault Recovery for Low-end Commodity Systems

Shuguang Feng, Shantanu Gupta, Amin Ansari, and Scott Mahlke (University of Michigan) and David August (Princeton University)

Formally Enhanced Runtime Verification to Ensure NoC Functional Correctness

Ritesh Parikh and Valeria Bertacco (University of Michigan)

Session Chair: Sudhakar Yalamanchili

Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits

Soontae kim (KAIST), Jesung Kim (LG Electronics), and Jongmin Lee and Seokin Hong (KAIST)

SHiP: Signature-Based Hit Predictor for High Performance Caching

Carole-Jean Wu (Princeton University), Aamer Jaleel (Intel Corporation), William Hasenplaugh (Intel Corporation / MIT), Margaret Martonosi (Princeton University), Simon Steely Jr (Intel Corporation), and Joel Emer (Intel Corporation / MIT)

PACMan: Prefetch-Aware Cache Management for High Performance Caching

Carole-Jean Wu (Princeton University), Aamer Jaleel (Intel Corporation), Margaret Martonosi (Princeton University), Simon Steely Jr (Intel Corporation), and Joel Emer (Intel Corporation / MIT)

Supporting Very Large Caches with Conventional Block Sizes

Gabriel H. Loh (AMD) and Mark D. Hill (University of Wisconsin)

Session Chair: Nikos Hardavellas

A Compile-Time Managed Multi-Level Register File Hierarchy

Mark Gebhart (The University of Texas at Austin), Stephen W. Keckler (NVIDIA and The University of Texas at Austin), and William J. Dally (NVIDIA and Stanford University)

SIMD Re-convergence at Thread Frontiers

Gregory Diamos, Andrew Kerr, Haicheng Wu, and Sudhakar Yalamanchili (Georgia Institute of Technology) and Benjamin Ashbaugh and Subramaniam Maiyuran (Intel)

A Data Layout Optimization Framework for NUCA-Based Multicores

Yuanrui Zhang, Wei Ding, Mahmut Kandemir, Jun Liu, and Ohyoung Jang (The Penn State University)