Race to Exascale: Challenges and Opportunities

Avinash Sodani

Abstract:

High performance community is racing to hit Exascale systems (10^18 FLOPS) before the end of the decade. This talk will present the goals, highlight various challenges and their implications for CPU design. It will also attempt to dispel some of the common myths on what architectural solutions are considered viable (or not) for Exascale by broader community.


Bio:

Avinash Sodani is a chief architect of a future Many Integrated Core (MIC) CPU at Intel. MIC is a many- core product line recently announced by Intel for highly parallel workloads. Prior to this role, Avinash was one of the primary architects of the Nehalem microprocessor (first Core i7/i5 processors) and worked as Server architect for Xeon line of products. Avinash has a PhD in computer architecture from Univ of Wisconsin-Madison. and a MS in Computer Science from the same university. He has a BTech in Computer Science from Indian Institute of Technology, Kharagpur.