Abstract
Immersive computing, including virtual, augmented, and mixed reality (collectively, extended reality or XR), integrates the virtual with the physical. Immersive systems enable AI to escape from the chatbot on a 2D screen into the 3D world around us, where it can perceive, understand, and act alongside the people who live and work there. AI, in turn, is making immersive systems more capable. We refer to the convergence of immersive computing and AI as immersive intelligence.
Immersive intelligence places demands on computer systems that are orders of magnitude beyond what current systems deliver: real-time inference over many interacting models, within the power envelope of all-day wearable devices, with quality ultimately judged by the human experience. Meeting these demands requires distributing immersive intelligence across the wearable, nearby devices, the edge, and the datacenter, and evaluating the resulting designs with new human-centric metrics. I will discuss recent work and what it suggests about the architecture of these systems, from the wearable to the datacenter, and about the opportunities ahead for our community. The talk will draw on ILLIXR, our open-source end-to-end XR system testbed, which supports distributed XR and first-of-their-kind AI-enabled XR capabilities, and on the IMMERSE Center for Immersive Computing at Illinois, which brings together research on immersive technologies, applications, and human experience.
Bio
Sarita Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois Urbana-Champaign. Her research interests span the system stack, ranging from hardware to applications, with a current focus on immersive intelligence, the convergence of immersive computing and AI. She directs the IMMERSE Center for Immersive Computing, which brings together expertise in immersive technologies, applications, and human experience to perform research, educate a new workforce, and build infrastructure to enable a new era of immersive computing. Her group released ILLIXR (Illinois Extended Reality testbed), an open-source end-to-end extended reality (XR) system and research testbed, to democratize XR research, development, and benchmarking. She led the XR section of SRC's MAPT 2.0 roadmap for the semiconductor industry. Her early work on data-race-free memory consistency models and later work on the memory models for the Java and C++ programming languages form the foundation for memory models used in most hardware and software systems today. She is also known for her work on heterogeneous architectures and software-driven hardware resiliency. She is a member of the American Academy of Arts and Sciences and a fellow of the ACM, IEEE, and AAAS. Her other honors include the ACM/IEEE-CS Ken Kennedy award, the ACM SIGARCH Maurice Wilkes award, the ACM SIGARCH Alan D. Berenbaum Distinguished Service award, the Anita Borg Institute Women of Vision award in innovation, a Sloan Foundation fellowship, the IIT Bombay Distinguished Alumnus/Alumna award, and several UIUC awards. As ACM SIGARCH chair, she co-founded the CARES movement, winner of the CRA distinguished service award, to address discrimination and harassment in computer science research events. She received her PhD from the University of Wisconsin-Madison and her B.Tech. from the Indian Institute of Technology Bombay.
Abstract
RISC-V has grown from a university project into a global open standard with a thriving ecosystem comprising hundreds of collaborating organizations, including most of the major companies in computing. This talk will describe the journey and lessons learned as we evolved the project over this period, and the current and future directions for RISC-V as it takes a central place in the computing industry.
Bio
Krste Asanovic is Professor Emeritus and a Professor of the Graduate School in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory ("Par Lab"), and led the ASPIRE Lab, and co-led the ADEPT Lab and Berkeley SLICE Lab. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He has led the RISC-V open ISA project at Berkeley from its inception in 2010 and co-founded the RISC-V Foundation in 2015, which has now become RISC-V International. He is now Chief Architect at RISC-V International. He also co-founded SiFive in 2015 to commercialize RISC-V processors, where he is Chief Architect. He is an ACM Fellow and an IEEE Fellow.
Abstract
What Meta delivers is not an accelerator. It is AI capacity in production — a workload running at scale, inside a cost and power envelope that works. Building that means building a complete system, and its pieces cannot be designed one at a time.
Meta's AI workloads are not homogeneous. The ranking and recommendation models behind personalized experiences do not want the same machine as large language models, and the models themselves change faster than any hardware generation can track. This talk is about how we build complete systems against that moving target, across five areas.
Silicon: architecting accelerators around our own models rather than the market's, then verifying and bringing them up for deployment. Software: mapping production PyTorch onto a non-GPU architecture, which determines whether the hardware's performance is reachable at all. Network: co-designing the interconnect with the accelerator so that communication scales alongside compute instead of competing with it. Power and cooling: removing heat at the densities modern accelerators demand, and designing datacenters around that constraint. Fleet: operating custom accelerators alongside merchant silicon while keeping datacenter capacity fully utilized.
These five are tightly coupled, and the talk will describe how we co-design across them, the challenges, the successes, and what remains open.
Bio
Prahlad Venkatapuram (Prahlad) has been in the semiconductor industry for over 3 decades. He is presently Vice President of Engineering, Infrastructure Silicon leading the development of in-house custom silicon at Meta. This work spans various domains such as Video Transcoding, AI/ML Training and Inference, Networking products (covering front-end and back-end custom NICs), and several interconnect technologies. Prior to Meta, Prahlad was Senior Director of Engineering at Qualcomm, supporting the development of Video and computer Vision Technology deployed in widely adopted Snapdragon Processors. Prahlad has previously held various engineering and engineering management positions at Nvidia, S3 Graphics, Cirrus Logic, AT&T Bell Laboratories, and National Semiconductor (Presently Texas Instruments) developing Silicon and systems for Automotive, Mobile, Compute and Communications market segments.