The 55th IEEE/ACM International Symposium on Microarchitecture® (MICRO) will conduct artifact evaluation (AE) for the second time. AE has become a common practice in the systems community (OSDI, PLDI, PACT, MLSys), and has recently been successfully introduced to the architecture community, with ASPLOS conducting AE in the last three years, and MICRO doing so as well in 2021. We invite the authors of accepted MICRO 2022 papers to submit their artifacts to be assessed based on the ACM Artifact Review and Badging policy. Note that this submission is voluntary and will not influence the final decision regarding the papers.
The authors of accepted papers at MICRO 2022 will be invited to submit their artifacts according to the established submission guidelines followed by previous conferences. Submission will be then reviewed according to the reviewing guidelines. Papers that successfully go through AE will receive a set of ACM badges of approval printed on the papers themselves and available as meta information in the ACM Digital Library (it is now possible to search for papers with specific badges in ACM DL). Authors of such papers will have an option to include a two-page-max artifact appendix to their camera-ready paper. The optional artifact appendix pages will be free of charge.
An artifact submission consists of two parts:
Please submit your artifact on our submission site. When you submit, please provide details about the artifact's software and hardware requirements. This will be extremely helpful for the Artifact Evaluation Committee to find suitable reviewers.
There are major benefits to introducing AE in our conferences.
| Artifact Evaluation Co-Chairs | Affiliation |
|---|---|
| Alexandros Daglis | Georgia Institute of Technology |
| Jason Lowe-Power | University of California, Davis |
| Committee Member | Affiliation |
|---|---|
| Sungwoo Ahn | Yonsei University Rutgers University |
| Vojtech Aschenbrenner | École Polytechnique Fédérale de Lausanne |
| Ashkan Asgharzadeh | University of Murcia |
| Abhishek Bhattacharyya | University of Wisconsin–Madison |
| Utpal Bora | University of Cambridge |
| Yue Dai | University of Pittsburgh |
| Poulami Das | Georgia Institute of Technology |
| Moumita Dey | Georgia Institute of Technology |
| Sankha Dutta | Pacific Northwest National Laboratory |
| S M Farabi Mahmud | Texas A&M University |
| Farzaneh | University of California, Santa Cruz |
| Boyuan Feng | University of California, Santa Barbara |
| Ivan Fernandez | University of Malaga |
| Eduardo José Gómez Hernández | University of Murcia |
| Christina Giannoula | National Technical University of Athens |
| Sneha Goenka | Stanford University |
| Ramyad Hadidi | SK hynix |
| Kashif Inayat | Incheon National University |
| Vighnesh Iyer | University of California, Berkeley |
| Vahid Janfaza | Texas A&M University |
| Aaron Jezghani | Georgia Institute of Technology |
| Adeeb Kabir | Rutgers University |
| Alireza Khadem | University of Michigan |
| Iacovos Kolokasis | University of Crete ICS–FORTH |
| Committee Member | Affiliation |
|---|---|
| Neeraj Ladkani | Microsoft Corporation |
| Bingyao Li | University of Pittsburgh |
| He Li | University of Cambridge |
| Shiyu Li | Duke University |
| Zhaoying Li | National University of Singapore |
| Zirui Li | Rutgers University |
| Jilan Lin | University of California, Santa Barbara |
| Sara Mahdizadeh Shahri | University of Michigan |
| Satvik Maurya | University of Wisconsin–Madison |
| Toluwanimi Odemuyiwa | UC Davis |
| Asmita Pal | University of Wisconsin–Madison |
| Zhewen Pan | University of Wisconsin–Madison |
| Benjamin Reidys | University of Illinois Urbana-Champaign |
| Xida Ren | University of Virginia |
| Ananda Samajdar | IBM Research |
| Akash Sridhar | Qualcomm |
| Cheng Wan | Rice University |
| Zishen Wan | Georgia Institute of Technology |
| Yuke Wang | University of California, Santa Barbara |
| Zheng Wang | UC Santa Barbara |
| Yuqi Xue | University of Illinois Urbana-Champaign |
| Bicheng Yang | Shanghai Jiao Tong University |
| Ziyang (Zion) Yang | Rice University |
| Haojie Ye | University of Michigan |
| Yicheng Zhang | University of California, Riverside |
| Ziyi Zhao | Rice University |
AE is an iterative process between authors and reviewers. It is a positive and constructive process that makes most artifacts much stronger. The authors can revise their submission and communicate with the reviewers through the submission website.
AE supports submissions with specialized hardware and simulators. The authors provide access to their specialized hardware through the submission website. ASPLOS 2021 evaluated artifacts include FPGA prototypes, ASICs, and specialized simulators.
AE supports artifacts with IP restrictions. In cases where some parts of the software/hardware stack cannot be shared, we let the authors provide direct access to their platform just to our evaluators so that they can perform measurements directly on those platforms. We have several successful cases of such an approach at ASPLOS 2021. In the end, authors can still receive functional and reproduced badges, but not the available badge.