MICRO 2022
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MICRO 2022
October 1–5, 2022
Workshops & Tutorials
Westin Chicago River North
Workshop & Tutorial Daily Schedule
On each workshop day, there will be:
30-minute coffee breaks at 10:30 AM and 3 PM
a 1-hour lunch at 12 PM
8:00 AM
CDT
– 12:00 PM
CDT
1:00 PM
CDT
– 5:00 PM
CDT
Sat
urday,
Oct
ober
1
PIM2
tutorial & workshop
Location: Riverfront
(
Ground Level
)
Combined Tutorial–Workshop on Processing-in-Memory
tutorial in the morning, workshop in the afternoon
CAV
workshop
Location: Washington
(
River Level -1
)
Compute Platforms for Autonomous Vehicles
OpenROAD
tutorial
Location: Washington
(
River Level -1
)
Open-Source ASIC Design for Computer Architects
AutoDL
tutorial
Location: Lincoln
(
River Level -1
)
Automated Tools for Fast Development of Deep Learning Networks and Accelerators
FPGA-DL
tutorial
Location: Lincoln
(
River Level -1
)
Deep Learning Optimized FPGA Architecture
FireSim & Chipyard
tutorial
Location: Jackson
(
River Level -1
)
End-to-End Architecture Research with RISC-V SoC Generators, Agile Test Chips, and FPGA-Accelerated Simulation
JOBS
workshop
Location: Grant
(
River Level -1
)
Accelerating Your Job Search
Vortex
tutorial
Location: Rogers
(
River Level -1
)
Open-Source RISC-V Based GPGPU: Vortex and Drone Applications on FPGA
HASP
workshop
Location: Rogers
(
River Level -1
)
Hardware and Architectural Support for Security and Privacy
CFU-Playground
tutorial
Canceled
Build Your Own Custom TinyML Processor
ADAPTOR
workshop
Canceled
Accelerator Design as Provably Correct Software
8:00 AM
CDT
– 12:00 PM
CDT
1:00 PM
CDT
– 5:00 PM
CDT
Sun
day,
Oct
ober
2
RoboARCH
workshop
Location: Riverfront
(
Ground Level
)
Robotics Acceleration with Computing Hardware
Cryo / Superconductor / Quantum
tutorial
Location: Grant
(
River Level -1
)
Full-Stack Simulation Framework for Cryogenic, Superconductor, and Fault-Tolerant Quantum Computing
WDDSA
workshop
Location: Grant
(
River Level -1
)
Workshop on Democratizing Domain-Specific Accelerators
FastPath
workshop
Location: Washington
(
River Level -1
)
Performance Analysis of Machine Learning Systems
NoCArc
workshop
Location: Jackson
(
River Level -1
)
15th International Workshop on Network on Chip Architectures
CWIDCA
workshop
Location: Astor
(
River Level -1
)
8th Career Workshop for Inclusion and Diversity in Computer Architecture
DISCC
workshop
Location: Rogers
(
River Level -1
)
Workshop on Data Integrity and Secure Cloud Computing
ACT
tutorial
Location: Rogers
(
River Level -1
)
Architectural Carbon Modeling Tool
EmergingBench
workshop
Location: Lincoln
(
River Level -1
)
Driving Architecture Specialization with Benchmarks for Emerging Applications
OverGen
tutorial
Location: Lincoln
(
River Level -1
)
A Full-Stack End-to-End Framework for Domain-Specific Accelerator Generation
