Abstract
The evolution of processor design in the last 50 years has taken a variety of paths, but the principles embodied in RISC design have been one of the most used approaches over the last 25 years. This talk will make the case that general-purpose RISC processors are likely to stay in the mainstream for the foreseeable future, along with other key technology developments that will influence the design of processors of the future. Having been an active participant in the RISC revolution since the term was coined in 1980, this presentation will review some of the salient achievements in the evolution of RISC until today, and talk about where the future will lead us. Most notable is that until recently, much computing has been done on only a single or small number of processor cores, but that we are entering a renaissance where access to thousands to millions of processor cores will be as common as a desktop computer is today. This talk will touch on some of the key technology advances that will enable our RISC based future, and make some predictions for what we can expect in the next decade.
Bio
Dave Ditzel is the founder and CTO of Esperanto Technologies, Inc., a company founded in 2014 that builds energy-efficient processors for AI and beyond based on the RISC-V instruction set. Prior to Esperanto, Dave spent six years at Intel Corporation as vice-president of Hybrid Computing, leading a team building a high-performance out-of-order processor using binary translation to run legacy x86 or ARM applications with improved energy efficiency. In 2007, he founded ThruChip Communications, to reduce IO energy between die by using wireless inductive communication. In 1995 Dave founded Transmeta Corporation, which developed low-power x86 compatible processors using Code Morphing binary translation on top of an energy-efficient VLIW architecture. Dave spent 10 years at Sun Microsystems as CTO for the SPARC Technology Business and led the development of the 64-bit SPARC ISA and various SPARC processors. Prior to Sun, Dave spent 10 years at AT&T Bell Laboratories, where he worked on a series of RISC processors optimized for the C programming language. Dave Ditzel was a graduate student under U.C. Berkeley Professor David Patterson and in 1980 they co-authored “The Case for the Reduced Instruction Set Computer”, which catalyzed the movement to RISC processors.
Abstract
As we enter the era of customized computing, where customized domain-specific accelerators (DSAs) are used extensively for performance and energy efficiency, ideally we would like to enable every programmer to offload the compute-intensive portion of his/her program to one or a set of DSAs, either pre-implemented in ASICs or synthesized on demand on programmable fabrics, such as FPGAs. High-level synthesis (HLS) made an important progress in this direction, but it still requires the programmer to provide various pragmas, such as loop unrolling, pipelining, and tiling, to define the microarchitecture of the accelerator, which is a challenging task to most software programmer. In this talk, we present our latest research on automated accelerator synthesis and customized computing on FPGAs, ranging from microarchitecture guided optimization, such as automated generation of highly optimized systolic arrays and stencil computation engines, to more general source-to-source transformation based on graph-based neural networks and meta learning, and finally to latency-insensitive system-level integration.
Bio
Jason Cong is the Volgenau Chair for Engineering Excellence Professor (and former Department Chair) at the UCLA Computer Science Department, with joint appointment from the Electrical Engineering Department, the director of Center for Domain-Specific Computing (CDSC), and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and highly scalable algorithms. He has close to 500 publications in these areas, including 16 best paper awards, three 10-Year Most Influential Paper Awards, and three papers inducted to the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs (renamed to Vivado HLS after Xilinx’s acquisition). He was elected an IEEE Fellow in 2000, ACM Fellow in 2008, the National Academy of Engineering in 2017, and the National Academy of Inventors in 2020. He is the recipient of the 2022 IEEE Robert Noyce Medal for fundamental contributions to electronic design automation and FPGA design methods.
What are the computer architecture and systems challenges, and what can/should the research community do about it? Global concern about climate change, and growing challenges with resource depletion and environmental damage make sustainability a core societal challenge with engagement of citizens, governments, and corporations around the world. Computing has become endemic, with digital electronics increasingly a part of manufactured devices from key fobs to automobiles to buildings to cloud datacenters, and our research community and industry has thrived as a result. As a consequence, computing's negative environmental impact is large and growing fast.
Specific topics will include - reducing scope 2 (operational) and scope 3 (embodied, downstream), accelerators, FPGAs, dark silicon, lifetime, datacenter design, and e-waste.
The panel will raise questions, provoke interesting research directions, and highlight industry, government, and funding opportunities.
Panelists
Abstract
While quantum computing promises to help solve some of the great challenges ahead, we are still in the early days of what will be possible. Today’s quantum computers enable exciting research and early development, however their small scale often limits what’s possible and leaves an eagerness to do more. Quantum at scale requires three foundational elements: an industrial scale quantum machine, the power of the cloud, and an ecosystem of innovators. Where does it all come together? Azure Quantum, Microsoft's platform for quantum innovation and exploration. Learn how Microsoft is architecting the scalable quantum machine and empowering innovators with quantum at scale by co-designing tools to optimize quantum solutions, to run small instances on today’s diverse and maturing quantum hardware, and prepare for tomorrow’s-scaled quantum compute.
Bio
Dr. Krysta Svore is a Distinguished Engineer and VP of Quantum Software at Microsoft. She is passionate about empowering people and organizations around the world with quantum computing and realizing a scaled quantum machine. Her team designs and delivers Azure Quantum, the most diverse cloud platform for quantum research and discovery, and is developing a comprehensive software stack for scalable quantum computing including languages, compilers, and mappings to quantum hardware. Her team designs open software including Q# and QIR. Dr. Svore has published over 70 refereed articles and filed over 30 patents. She is a fellow of the American Association for the Advancement of Science and of Washington State Academy of Sciences. She won the 2010 Yahoo! Learning to Rank Challenge with a team of colleagues, received an ACM Best of 2013 Notable Article award, and was recognized as one of Business Insider Most Powerful Female Engineers of 2018. A Kavli fellow of the National Academy of Sciences, she also serves as an advisor to the National Quantum Initiative, the Advanced Scientific Computing Advisory Committee of the Department of Energy, and the ISAT Committee of DARPA, in addition to numerous other quantum centers and initiatives globally.