The 54th IEEE/ACM International Symposium on Microarchitecture® (MICRO) introduces artifact evaluation (AE) for the first time. AE has become a common practice in the systems community (OSDI, PLDI, PACT, MLSys), and recently, ASPLOS has also successfully introduced AE in the last two years (in ASPLOS 2021 and ASPLOS 2020). We invite the authors of accepted MICRO 2021 papers to submit their artifacts to be assessed based on the ACM Artifact Review and Badging policy. Note that this submission is voluntary and will not influence the final decision regarding the papers.
The authors of accepted papers at MICRO 2021 will be invited to submit their artifacts according to the established submission guidelines followed by previous conferences. Submission will be then reviewed according to the reviewing guidelines. Papers that successfully go through AE will receive a set of ACM badges of approval printed on the papers themselves and available as meta information in the ACM Digital Library (it is now possible to search for papers with specific badges in ACM DL). Authors of such papers will have an option to include a two-page-max artifact appendix to their camera-ready paper. The optional artifact appendix pages will be free of charge.
An artifact submission consists of two parts:
Please submit your artifact on our submission site. When you submit, please provide details about the artifact's software and hardware requirements. This will be extremely helpful for the Artifact Evaluation Committee to find suitable reviewers.
There are major benefits to introducing AE in our conferences.
|Artifact Evaluation Co-Chairs||Affiliation|
|Samira Khan||University of Virginia|
|Gennady Pekhimenko||University of Toronto|
|Sihang Liu||University of Virginia|
AE is an iterative process between authors and reviewers. It is a positive and constructive process that makes most artifacts much stronger. The authors can revise their submission and communicate with the reviewers through the submission website.
AE supports submissions with specialized hardware and simulators. The authors provide access to their specialized hardware through the submission website. ASPLOS 2021 evaluated artifacts include FPGA prototypes, ASICs, and specialized simulators.
AE supports artifacts with IP restrictions. In cases where some parts of the software/hardware stack cannot be shared, we let the authors provide direct access to their platform just to our evaluators so that they can perform measurements directly on those platforms. We have several successful cases of such an approach at ASPLOS 2021. In the end, authors can still receive functional and reproduced badges, but not the available badge.