The 48th Annual IEEE/ACM International Symposium on Microarchitecture, 2015

Future Processor/Memory System Architecture


    J. Thomas Pawlowski


We stand at the most exciting time in the history of processor and memory development. All can see the end of CMOS logic scaling, the only debate being at which node. “Moore’s Law”, if ever it in fact worked, has surely ended though scaling continues at a slower pace. This has spawned exciting debates and many intelligent discussions proposing different architecture directions. This talk presents a challenging memory-centric view of future processor/memory and storage systems. We examine the reality of scaling in both CMOS and memory technologies. From this analysis new directions become apparent. Not that these issues are exciting enough, a ground-breaking new memory technology is also entering this mix. In light of these developments we examine the roles of the logic and memory technologies and suggest significant changes that are an inevitable part of our future. What are the real walls? What is the balance between use of CMOS logic and memory technologies as we further scale? What of silicon photonics? We will briefly discuss new products which are inspired by the answers to these questions. We will examine the big picture: the future of processor/memory systems and the relationship between the two prime components. The necessity of memory abstraction will be demonstrated. New possibilities will be explored along with implications to the future of computing and elements we need to make this future a reality: building blocks which will change the face of computing.

Biography – J. Thomas Pawlowski 

J. Thomas Pawlowski is a Fellow and Chief Technologist with Micron’s Architecture Development Group. His responsibilities include evaluating new technologies and investments, exploring new memory and system architectures, and providing guidance to many technical teams, both internally and external to Micron.

Mr. Pawlowski’s experience includes the creation or co-creation of numerous groundbreaking memory architectures and concepts including: synchronous burst pipelined SRAM; hierarchical cache systems; Zero Bus Turnaround SRAM; abstracted memory; the first double data rate memory (starting with SRAM and extending to DRAM and NAND technologies); Pseudo-Static RAM; high-speed NAND; the first double address rate memory; the first quad data rate memory; the first multi-channel memory; memories on SERDES buses; RLDRAM (the first DRAM to exceed SRAM performance); refresh and error correction schemes for memory subsystems; the first 3D memory concept; root hardware architecture of Micron’s newly nondeterministic Finite Automata Processor; abstraction protocols, new ECC concepts, 3D Xpoint system architectures and other projects to be announced.

Mr. Pawlowski earned a bachelor of applied science degree in electrical engineering, summa cum laude, from the University of Waterloo in Canada. He has well over 100 U.S. and in-flight patents and serves on several advisory boards and conference program committees.

In his spare time, Mr. Pawlowski designs and builds loudspeakers, simulation tools, fabrication tools, and he has completed 68% of the design and fabrication of a high-efficiency electric concept car.

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