The 41st Annual IEEE/ACM International Symposium on Microarchitecture, 2008

Conference Program

Monday, November 10, 2008
8:30-10:00	Opening (Spazio Como)
	Keynote1 Microarchitecture in the System-level Integration Era Charles R. Moore, Senior Fellow, AMD
10:00-10:30	Coffee Break
10:30-12:00	Session 1P (Spazio Como) Instruction-Level Parallelism Chair: Norm Jouppi, HP Labs
	Temporal Instruction Fetch Streaming Michael Ferdman (Carnegie Mellon University) Thomas F. Wenisch (University of Michigan) Anastasia Ailamaki (Carnegie Mellon University and EPFL) Babak Falsafi (Carnegie Mellon University and EPFL) Andreas Moshovos (University of Toronto)
	A Distributed Processor State Management Architecture for Large-Window Processors Isidro González (DAC-UPC) Marco Galluzzi (DAC-UPC) Alex Veidenbaum (ICS-UCI) Marco Antonio Ramírez (CIC-IPN) Adrián Cristal (BSC) Mateo Valero (DAC-UPC / BSC)
	Strategies for Mapping Data Flow Blocks to Distributed Hardware Behnam Robatmili (University of Texas at Austin, Computer Science Department) Katherine E. Coons (University of Texas at Austin, Computer Science Department) Doug Burger (Microsoft Research) Kathryn S. McKinley (University of Texas at Austin, Computer Science Department)
12:00-13:30	Lunch
13:30-15:00	Session 2P (Spazio Como) Cache Coherence and Cache Modeling Chair: Karu Sankaralingam, Univ. of Wisconsin
	Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Natalie D. Enright Jerger (University of Wisconsin - Madison) Mikko Lipasti (University of Wisconsin - Madison) Li-Shiuan Peh (Princeton University)
	Token Tenure: PATCHing Token Counting Using Directory-Based Cache Coherence Arun Raghavan (University of Pennsylvania) Colin Blundell (University of Pennsylvania) Milo M. K. Martin (University of Pennsylvania)
	Hybrid Analytical Modeling of Pending Cache Hits, Data Prefetching, and MSHRs Xi E. Chen (University of British Columbia) Tor M. Aamodt (University of British Columbia)
15:00-15:30	Coffee Break
15:30-17:00	Session 3P (Spazio Como) Cache Architectures for Security and Availability Chair: Todd Austin, Univ. of Michigan
	Implementing High Availability Memory with a Duplication Cache Nidhi Aggarwal (UW Madison) James E. Smith (Google) Norman P. Jouppi (HP Labs) Kewal K. Saluja (UW Madison) Parthasarathy Ranganathan (HP Labs)
	A Novel Cache Architecture with Enhanced Performance and Security Zhenghong Wang (Princeton University) Ruby B. Lee (Princeton University)
	A Small Cache of Large Ranges: Hardware Methods for Efficiently Searching, Storing, and Updating Big Dataflow Tags Mohit Tiwari (UCSB) Banit Agrawal (UCSB) Shashi Mysore (UCSB) Jonathan K Valamehr (UCSB) Timothy Sherwood (UCSB)
17:00-18:00	Special Session (Spazio Como) "EU-US Funded Research Opportunities and Trends in Computing Systems".
21:00-23:00	Business Meeting. Villa Monastero
Tuesday, November 11, 2008
8:30-10:00	Keynote 2 (Spazio Como) Architectures and Algorithms for Millisecond-Scale Molecular Dynamics Simulations of Proteins David E. Shaw, D. E. Shaw Research and Columbia University
10:00-10:30	Coffee Break
10:30-12:30	Session 4A (Villa Monastero) Reliability, Availability, Security Chair: Babak Falsafi, EPFL
	SHARK: Architectural Support for Autonomic Protection Against Stealth by Rootkit Exploits Vikas R. Vasisht (Georgia Tech) Hsien-Hsin S. Lee (Georgia Tech)
	Testudo: Heavyweight Security Analysis via Statistical Sampling Joseph L. Greathouse (University of Michigan) Ilya Wagner (University of Michigan) David A. Ramos (University of Michigan) Gautam Bhatnagar (University of Michigan) Todd Austin (University of Michigan) Valeria Bertacco (University of Michigan) Seth Pettie (University of Michigan)
	Facelift: Hiding and Slowing Down Aging in Multicores Abhishek Tiwari (University of Illinois at Urbana-Champaign) Josep Torrellas (University of Illinois at Urbana-Champaign)
	The StageNet Fabric for Constructing Resilient Multicore Systems Shantanu Gupta (University of Michigan, Ann Arbor) Shuguang Feng (University of Michigan, Ann Arbor) Amin Ansari (University of Michigan, Ann Arbor) Jason Blome (University of Michigan, Ann Arbor) Scott Mahlke (University of Michigan, Ann Arbor)
10:30-12:30	Session 4B (Spazio Como) Embedded and Special Purpose Architectures Chair: Glenn Farrall, Infineon
	From Soda to Scotch: The Evolution of a Wireless Baseband Processor Mark Woh (University of Michigan at Ann Arbor) Yuan Lin (University of Michigan at Ann Arbor) Sangwon Seo (University of Michigan at Ann Arbor) Scott Mahlke (University of Michigan at Ann Arbor) Trevor Mudge (University of Michigan at Ann Arbor) Chaitali Chakrabarti (Arizona State University) Richard Bruce (ARM Ltd.) Danny Kershaw (ARM Ltd.) Alastair Reid (ARM Ltd.) Mladen Wilder (ARM Ltd.) Krisztian Flautner (ARM Ltd.)
	Tradeoffs in Designing Accelerator Architectures for Visual Computing Aqeel Mahesri (UIUC) Daniel Johnson (UIUC) Neal Crago (UIUC) Sanjay J. Patel (UIUC)
	Toward A Multicore Architecture for Real-time Ray-Tracing Venkatraman Govindaraju (University of Wisconsin-Madison) Peter Djeu (University of Texas at Austin) Karthikeyan Sankaralingam (University of Wisconsin-Madison) Mary Vernon (University of Wisconsin-Madison) William R. Mark (University of Texas at Austin)
	Power to the People: Leveraging Human Physiological Traits to Control Microprocessor Frequency Alex Shye (Northwestern University) Yan Pan (Northwestern University) Ben Scholbrock (Northwestern University) J. Scott Miller (Northwestern University) Gokhan Memik (Northwestern University) Peter A. Dinda (Northwestern University) Robert P. Dick (Northwestern University)
12:30-14:00	Lunch
14:00-15:30	Session 5A (Villa Monastero) Memory and Cache Architectures Chair: Sanjay Patel, UIUC
	Prefetch-Aware DRAM Controllers Chang Joo Lee (The University of Texas at Austin) Onur Mutlu (Microsoft Research / Carnegie Mellon University) Veynu Narasiman (The University of Texas at Austin) Yale N. Patt (The University of Texas at Austin)
	Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency Hongzhong Zheng (University of Illinois at Chicago) Jiang Lin (Iowa State University) Zhao Zhang (Iowa State University) Eugene Gorbatov (Intel Corp.) Howard David (Intel Corp.) Zhichun Zhu (University of Illinois at Chicago)
	Cache Bursts: A New Approach for Eliminating Dead Blocks and Increasing Cache Efficiency Haiming Liu (University of Texas at Austin) Michael Ferdman (Carnegie Mellon University) Jaehyuk Huh (AMD) Doug Burger (Microsoft Research)
14:00-15:30	Session 5B (Spazio Como) Transactions and Runtime Systems Chair: Jim Denhert, Google
	Notary: Hardware Techniques to Enhance Signatures Luke Yen (UW Madison) Stark C. Draper (UW Madison) Mark D. Hill (UW Madison)
	Dependence-Aware Transactional Memory for Increased Concurrency Hany E. Ramadan (University of Texas at Austin) Christopher J. Rossbach (University of Texas at Austin) Emmett Witchel (University of Texas at Austin)
	Reducing the Harmful Effects of Last-Level Cache Polluters with an OS-Level, Software-Only Pollute Buffer Livio Soares (University of Toronto) David Tam (University of Toronto) Michael Stumm (University of Toronto)
15:30-16:00	Coffee Break
16:00-17:30	Session 6A (Villa Monastero) Modeling, Simulation and Verification Chair: Tom Conte, Georgia Institute of Technology
	CPR: Composable Performance Regression for Scalable Multiprocessor Models Benjamin C. Lee (Harvard University / Microsoft Research) Jamison Collins (Intel Corporation) Hong Wang (Intel Corporation) David Brooks (Harvard University)
	Online Design Bug Detection: RTL-Level Analysis, Flexible Mechanisms, and Evaluation Kypros Constantinides (University of Michigan) Onur Mutlu (Microsoft Research) Todd Austin (University of Michigan)
	Verification of Chip Multiprocessor Memory Systems Using A Relaxed Scoreboard Ofer Shacham (Stanford University) Megan Wachs (Stanford University) Alex Solomatnikov (Stanford University) Amin Firoozshahian (Stanford University) Stephen Richardson (Stanford University) Mark Horowitz (Stanford University)
16:00-17:30	Session 6B (Spazio Como) Multicore and Multithreading Chair: Yale Patt, Univ. of Texas Austin
	A Performance-Correctness Explicitly-Decoupled Architecture Alok Garg (University of Rochester) Michael Huang (University of Rochester)
	Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach Ramazan Bitirgen (Cornell University) Engin Ipek (Microsoft Research) José F. Martínez (Cornell University)
	Copy Or Discard Execution Model For Speculative Parallelization On Multicores Chen Tian (University of California at Riverside, CSE Dept.) Min Feng (University of California at Riverside, CSE Dept.) Vijay Nagarajan (University of California at Riverside, CSE Dept.) Rajiv Gupta (University of California at Riverside, CSE Dept.)
17:45-22:00	Como Guided Tour and Gala Dinner at Società del Casino in Como (from 20:00 to 22:00)
Wednesday, November 12, 2008
8:30-10:30	Session 7A (Villa Monastero) Interconnects Chair: Krisztian Flautner, ARM
	Token Flow Control Amit Kumar (Princeton University) Li-Shiuan Peh (Princeton University) Niraj K. Jha (Princeton University)
	Adaptive Data Compression for High-Performance Low-Power On-Chip Networks Yuho Jin (Texas A&M University) Ki Hwan Yum (University of Texas, San Antonio) Eun Jung Kim (Texas A&M University)
	Efficient Unicast and Multicast Support for CMPs Samuel Rodrigo (UPV) José Flich (UPV) José Duato (UPV) Mark Hummel (AMD fellow)
	Power Reduction of CMP Communication Networks via RF-Interconnects M-C. Frank Chang (UCLA Electrical Engineering) Jason Cong (UCLA Computer Science) Adam Kaplan (UCLA Computer Science) Chunyue Liu (UCLA Computer Science) Mishali Naik (UCLA Computer Science) Jagannath Premkumar (UCLA Computer Science) Glenn Reinman (UCLA Computer Science) Eran Socher (UCLA Electrical Engineering) Sai-Wang Tam (UCLA Electrical Engineering)
8:30-10:30	Session 7B (Spazio Como) Process Variation Chair: Dave Albonesi, Cornell University
	Evaluating the Effects of Cache Redundancy on Profit Abhishek Das (Northwestern University) Berkin Ozisikylmaz (Northwestern University) Serkan Ozdemir (Northwestern University) Gokhan Memik (Northwestern University) Joseph Zambreno (Northwestern University) Alok Choudhary (Northwestern University)
	NBTI Tolerant Microarchitecture Design in the Presence of Process Variation Xin Fu (University of Florida) Tao Li (University of Florida) Jose Fortes (University of Florida)
	Shapeshifter: Dynamically Changing Pipeline Width and Speed to Address Process Variations Eric Chun (Purdue University) Zeshan Chishti (Intel) T. N. Vijaykumar (Purdue University)
	EVAL: Utilizing Processors with Variation-Induced Timing Errors Smruti Sarangi (IBM) Brian Greskamp (University of Illinois) Abhishek Tiwari (University of Illinois) Josep Torrellas (University of Illinois)
10:30-11:00	Coffee Break
11:00-12:30	Session 8P (Spazio Como) Circuits and Microarchitectures Chair: Bill Mangione-Smith, Intellectual Ventures
	Microarchitecture Soft Error Vulnerability Characterization and Mitigation under 3D Integration Technology Wangyuan Zhang (University of Florida) Tao Li (University of Florida)
	Low-Power, High-Performance Analog Neural Branch Prediction Renée St. Amant (The University of Texas at Austin) Daniel A. Jiménez (The University of Texas at San Antonio) Doug Burger (Microsoft Research)
	Reconfigurable Energy Efficient Near Threshold Cache Architectures Ronald Dreslinski (University of Michigan) Gregory K. Chen (University of Michigan) Trevor Mudge (University of Michigan) David Blaauw (University of Michigan) Dennis Sylvester (University of Michigan) Krisztian Flautner (ARM)
12:30-13:00	Closing Session and Awards (Spazio Como)
14:30-17:30	Lake Como Tour The tour will start at 2:30pm from Tavernola (close to the GRAND HOTEL DI COMO) and will pass close to the cities of Cernobbio, Pizzo, Moltrasio, Laglio, Balbianello and Villa Carlotta; The boat will turn in front of Bellagio (without any landing) after 1h30m of cruise and it will came back to Como on the other side of the lake passing close to the small cities of San Giovanni, Lezzeno, Nesso, Villa Pliniana, Torno and Blevio.