OpenSPARC - A Scalable Chip Multi-Threading Design

Paul Jordan, Senior Staff Engineer
David Weaver, UltraSPARC Architect
Jhy-Chun Wang, Senior Staff Engineer

Abstract: Chip Multi-Threading is the new wave that is sweeping this decade. It is no longer a theoretical discussion topic but one where revolutionary products with CMT will permeate every aspect of computing infrastructure. So, how does Academia innovate on this new frontier? Sun Microsystems has contributed to the open-source community a large state-of-the-art design called the, OpenSPARC T1. This new open source version of the UltraSPARC T1 design is a 64 bit, 32 threaded processor design available at no charge. For the first time in history, developers gain access to the chip multi-threading (CMT) technology unique to the UltraSPARC T1 processor, which is released under the GNU General Public License (GPL). The specifications, verilog RTL, verification environment, diagnostic test suite, SPARC Architecture Model, instruction accurate simulator, OBP, hypervisor and Solaris OS image are all made available.

Also been planning for release is the OpenSPARC T2 design based on the UltraSPARC T2 processor that was recently announced. This state-of-art CMT design has 8 cores with 8 threads per core and a floating point unit per core. An overview of the architecture will be presented.

This tutorial will provide the background for building systems and software using the OpenSPARC design. Members of the development team will present on the following:

Paul Jordan has 16 years of microprocessor research and design experience. As a Senior Staff Engineer with Sun Microsystems, Paul Jordan developed the microarchitecture and logic design of the Trap Logic and Memory Management Units of the UltraSPARC T2's processor core. Prior to Sun, he led a multidisciplinary team in developing the microarchitecture, design, integration, and verification of the Fixed Point Unit of the Power4 processor at IBM. Paul Jordan also contributed to the design and implementation of the 620 and Power2 processors while at IBM. Paul Jordan holds 15 patents and has seven pending patent applications. He received a BSEE from Rice University in 1990.

David Weaver has been involved with SPARC for over 20 years. He hired on at Sun to lead the SPARC software effort (compilers, OS port, etc) and became active on Sun's SPARC Architeture Committee. He has been responsible for every published SPARC Architecture specfication, including SPARC V8, SPARC V9, UltraSPARC Architecture 2005, and UltraSPARC Architecture 2007. He's charged with overseeing consistency and binary compatibility of Sun's SPARC implementations, across implementations and over time. He has served as chair of SPARC International's Architecture Committee, currently serves on the OpenSPARC Governance Board, and holds a patent for an innovation in processor architecture. Outside of Sun, Dave is an avid photographer, instrument-rated private pilot, and father of two.

Jhy-Chun Wang is a senior staff engineer with Sun Microsystems, his responsibilities include CPU architecture reference model, full-system simulation model, benchmarking and performance analysis. Jhy-Chun has a Ph.D. degree in computer science from Syracuse University, USA.