MICRO-35 Advance Program

Monday, November 18, 2002

Tutorials/Workshops

8:00am-6:00pm

• Morning Tutorial (Track 1):  Asynchronous Microprocessor Design
  Chairs: Alain J. Martin, Mika Nystroem (Caltech)
• Afternoon Tutorial (Track 1):  Tutorial on Partially Asynchronous Microprocessors (PAMs)
  Chairs: Diana Marculescu (CMU), David Albonesi (University. of Rochester), and Pradip Bose (IBM)
• Afternoon Tutorial (Track 2):  From Molecules to Computers
  Chair: Seth Copen Goldstein (CMU)
• 2nd Workshop on EPIC Architectures and Compiler Technology
  Chairs: David August (Princeton University), Dan Connors (University of Colorado), Carole Dulong (Intel Corporation), and Rick Hank (Hewlett-Packard)
• 4th Workshop on Media and Stream Processors
  Chairs: Vipin Chaudhary (Wayne State University, Cradle Technologies), Jason Fritts (Washington University), and Alex Dean (North Carolina State University)

Tuesday, November 19, 2002

Tutorials/Workshops

8:00am-6:00pm

• Morning Tutorial (Track 1):  Thermal Management Issues for Microprocessors
  Chairs: Kevin Skadron, Mircia Stan (University of Virgina), and David Brooks (Harvard University)
• Afternoon Tutorial (Track 1):  An Introduction to Network Processor Research and Design
  Chair: Patrick Crowley (University of Washington)
• Morning Tutorial (Track 2):  Open Research Compiler (ORC) 2.0 and Tuning Performance on Itanium
  Chairs: Roy Ju, Sun Chan (Intel Corporation), Chengyong Wu (ICT, CAS), Tao Huang (Intel Corporation)
• Afternoon Tutorial (Track2):  Simics Microarchitect's Toolset
  Chair: Peter Magnusson (Virtutech)
• 6th Workshop on Multi-threaded Execution, Architecture and Compilation
  Chairs: Antonio Gonzalez (UPC Barcelona and Intel Corporation), Walid Najjar (University of California, Riverside), and Dean Tullsen (University of California, San Diego)
• 1st Workshop on Application Specific Processors (WASP)
  Chairs: Alex Orailoglu (University of California, San Diego)

Wednesday, November 20, 2002

Welcome and Keynote I

8:00am-9:15am, Wednesday November 20

Welcome

8:00am-8:15am

• Kemal Ebcioğlu, General Chair
• Scott Mahlke and Bob Rau, Program Co-chairs

Keynote I

8:15am-9:15am

• Tilak Agerwala
  Systems Trends and their Impact on Future Microprocessor Design
  Vice President, Systems
  IBM Research

Break

9:15am-9:45am

Session 1: Superscalar Design
Ronny Ronen (Intel Corporation), chair

9:45am-11:45am, Wednesday November 20

• Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors
  Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois)
• Characterizing and Predicting Value Degree of Use
  J. Adam Butts and Gurindar S. Sohi (University of Wisconsin)
• Hierarchical Scheduling Windows
  Edward Brekelbaum, Jeff Rupley, Chris Wilkerson, and Bryan Black (Intel Corporation)
• Three Extensions to Register Integration
  Vlad Petric, Anne Bracy, and Amir Roth (University of Pennsylvania)

Lunch

11:45am-1:00pm

Session 2: Multithreading I
Yale Patt (University of Texas, Austin), chair

1:00pm-3:00pm, Wednesday November 20

• Instruction Fetch Deferral using Static Slack
  Gregory A. Muthler, David Crowe, Sanjay J. Patel, and Steven S. Lumetta (University of Illinois)
• Pointer Cache Assisted Prefetching
  Jamison Collins, Suleyman Sair, Brad Calder, and Dean M. Tullsen (University of California, San Diego)
• Microarchitectural Support for Precomputation Microthreads
  Robert S. Chappell (University of Michigan), Francis Tseng (University of Texas, Austin), Adi Yoaz (Intel Corporation), and Yale N. Patt (University of Texas, Austin)
• Master/Slave Speculative Parallelization
  Craig Zilles (University of Illinois) and Guri Sohi (University of Wisconsin)

Break

3:00pm-3:30pm

Session 3: Compiler Scheduling
Brad Calder (University of California, San Diego), chair

3:30pm-5:30pm, Wednesday November 20

• Reduced Code Size Modulo Scheduling in the Absence of Hardware Support
  Josep Llosa (UPC Barcelona) and Stefan Freudenberger (Hewlett-Packard)
• Convergent Scheduling
  Walter Lee, Diego Puppin, Shane Swenson and Saman Amarasinghe(MIT)
• Effective Instruction Scheduling Techniques for an Interleaved Cache Clustered VLIW Processor
  Enric Gibert (UPC Barcelona), Jesús Sánchez, and Antonio González (UPC Barcelona and Intel Corporation)
• Compiler Managed Micro-cache Bypassing for High Performance EPIC Processors
  Youfeng Wu, Ryan Rakvic, Li-Ling Chen, Chyi-Chang Miao, George Chrysos, Jesse Fang (Intel Corporation)

Break

5:30pm-6:00pm

Session 4: Register File and Memory System Design
Roy Ju (Intel Corporation), chair

6:00pm-7:30pm, Wednesday November 20

• Three-dimensional Memory Vectorization for High Bandwidth Media Memory Systems
  Jesús Corbal, Roger Espasa, and Mateo Valero (UPC Barcelona)
• Dynamic Addressing Memory Arrays with Physical Locality
  Steven K. Hsu (Oregon State University and Intel Corporation), Shih-Lien Lu (Intel Corporation), Shih-Chang Lai (Oregon State University), Ram Krishnamurthy, and Konrad Lai (Intel Corporation)
• Reducing Register Ports for Higher Speed and Lower Energy
  Il Park, Michael D. Powell, and T. N. Vijaykumar (Purdue University)

Banquet

8:00pm-11:00pm

The banquet will take place at:

The Feriye Restaurant
Ciragan Cad. No: 124, Ortaköy - 80700 ISTANBUL
Tel: +90 (212) 227 22 16 (or +90 (212) 227 22 17)

Thursday, November 21, 2002

Session 5: Energy Efficient Memory Systems
Bill Mangione-Smith (UCLA), chair

8:00am-10:00am, Thursday November 21

• Generating Physical Addresses Directly for Saving Instruction TLB Energy
  Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul Kandiraju, and Guangyu Chen (Pennsylvania State University)
• Energy Efficient Frequent Value Cache Design
  Jun Yang (University of California, Riverside) and Rajiv Gupta (University of Arizona)
• Compiler-Directed Instruction Cache Leakage Optimization
  Wei Zhang, Jie Hu, Vijay Degalahal, Mahmut Kandemir, N. Vijaykrishnan, and Mary J. Irwin (Pennsylvania State University)
• Drowsy Instruction Caches - Leakage Power Reduction using Dynamic Voltage Scaling
  Nam Sung Kim (University of Michigan), Krisztián Flautner (ARM), David Blaauw, and Trevor Mudge (University of Michigan)

Break

10:00am-10:30am

Session 6: Compilation and Run-time Systems
Jim Dehnert (Transmeta), chair

10:30am-12:00pm, Thursday November 21

• Vacuum Packing: Extracting Hardware-Detected Program Phases for Post-Link Optimization
  Ronald D. Barnes, Erik M. Nystrom, Matthew C. Merten, and Wen-mei W. Hwu (University of Illinois)
• A Faster Optimal Register Allocator
  Changqing Fu and Kent Wilken (University of California, Davis)
• DELI: A New Run-time Control Point
  Giuseppe Desoli (STMicroelectronics), Nikolay Mateev (Hewlett-Packard), Evelyn Duesterwald (IBM), Paolo Faraboschi, and Joseph A. Fisher (Hewlett-Packard)

Break

12:00pm-12:25pm

Excursion in Istanbul

12:25pm-6:30pm, Thursday November 21

Busses will leave the Hilton at 12:25PM. Box lunches will be provided. We will first visit famous landmarks of Istanbul: the (Byzantine) Hippodrome, the Blue Mosque and the Hagia Sophia. This will be followed by a boat tour on the Bosphorus.

MICRO Business Meeting

9:00pm-11:00pm

Friday, November 22, 2002

Keynote II

8:00am-9:00am, Friday November 22

• Justin R. Rattner
  Right Hand Turn for Power Efficient Computing
  Intel Fellow, Enterprise Platforms Group 
  Director, Microprocessor Research, Intel Labs

Break

9:00am-9:30am

Session 7: Simulation and Architecture Evaluation
Antonio Gonzalez (UPC Barcelona), chair

9:30am-11:30am, Friday November 22

• Microarchitectural Exploration with Liberty
  Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, and David I. August (Princeton University)
• Vector Vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks
  Christoforos Kozyrakis (Stanford University) and David Patterson (University of California, Berkeley)
• Orion: A Power-Performance Simulator for Interconnection Networks
  Hang-Sheng Wang, Xinping Zhu, Li-Shiuan Peh, and Sharad Malik (Princeton University)
• A Framework and Analysis of Modern Graphics Architectures for General-Purpose Computing
  Christopher J. Thompson, Sahngyun Hahn, and Mark Oskin (University of Washington)

Lunch

11:30am-1:00pm

Invited NSF Speaker

11:55am-12:20pm, Friday November 22

• Prof. A. Yavuz Oruc
  The Role of NSF in Computer Architecture Research
  University of Maryland
  Director, Computer Systems Architecture Program, 2000-2002
  National Science Foundation

Session 8: Energy Aware Design
Evelyn Duesterwald (IBM Corporation), chair

1:00pm-3:00pm, Friday November 22

• Managing Static Leakage Energy in Microprocessor Functional Units
  Steven Dropsho, Volkan Kurşun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman (University of Rochester)
• Optimizing Pipelines for Power and Performance
  Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, and Philip G Emma (IBM)
• Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses
  Kohinoor Basu, Alok Choudhary, Jay Pisharath (Northwestern University), and Mahmut Kandemir (Pennsylvania State University)
• Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture
  Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Grigorios Magklis, Sandhya Dwarkadas, and Michael L. Scott (University of Rochester)

Break

3:00pm-3:30pm

Session 9: Superscalar Microarchitecture
Sanjay Patel (University of Illinois), chair

3:30pm-5:00pm, Friday November 22

• Fetching Instruction Streams
  Alex Ramirez, Oliverio J. Santana, Josep L. Larriba-Pey and Mateo Valero (UPC Barcelona)
• Register Write Specialization Register Read Specialization: A Path to Complexity-Effective Wide-Issue Superscalar Processors
  André Seznec (IRISA/INRIA), Eric Toullec (IRISA, Université de Rennes I), and Olivier Rochecouste (IRISA/INRIA)
• Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth
  Gabriel H. Loh (Yale University)

Break

5:00pm-5:30pm

Session 10: Multithreading II
Matt Farrens (University of California, Davis), chair

5:30pm-7:00pm, Friday November 22

• Microarchitectural Denial of Service: Insuring Microarchitectural Fairness
  Dirk Grunwald and Soraya Ghiasi (University of Colorado)
• Compiling for Instruction Cache Performance on a Multithreaded Architecture
  Rakesh Kumar and Dean M. Tullsen (University of California, San Diego)
• A Quantitative Framework for Automated Pre-Execution Thread Selection
  Amir Roth (University of Pennsylvania) and Gurindar S. Sohi (University of Wisconsin)

Closing and Awards

7:00pm-7:30pm