Three Extensions To Register Integration
Authors:
Abstract:
Register integration (or just integration) is a register
renaming discipline that implements instruction reuse via
physical register sharing. Initially developed to perform
squash reuse, the integration mechanism can exploit
more reuse scenarios. Here, we describe three extensions
to the original design that expand its applicability and
boost its performance impact. First, we extend squash
reuse to general reuse. Whereas squash reuse maintains
the concept of an instruction instance "owning" its out-put
register, we allow multiple instructions to simulta-neously
share a single register. Next, we replace the PC-indexing
scheme with an opcode-based indexing scheme that exposes more integration opportunities. Finally, we introduce an extension called reverse integration in which we speculatively create integration entries for the
inverses of operations for instance, when renaming an
add, we create an entry for the inverse subtract. Reverse
integration allows us to reuse operations that the pro-gram
itself has not executed yet. We use reverse integra-tion
to implement speculative memory bypassing for
stack-pointer based loads (register fills and restores).
Our evaluation shows that these extensions increase
the integration rate the number of retired instructions
that integrate older results and bypass the execution
engine to an average of 15% on the SPEC2000 integer
benchmarks. On a 4-way superscalar processor with an
aggressive memory system, this translates into an aver-age
IPC improvement of 7%. The fact that integrating
instructions completely bypass the execution engine
raises the possibility of using integration as a low-com-plexity
substitute for execution bandwidth and issue buff-ering.
Our experiments show that such a trade-off is
possible, enabling a range of IPC/complexity designs.