General Chair
Yale Patt, UT-Austin

Program Chairs
Josh Fisher, HP Labs

Paolo Faraboschi, HP Labs

Workshop Chair
Scott Mahlke, University of Michigan

Local Arrangements
Steve Keckler, UT-Austin

Publicity Chair
Dan Connors, Univ. of Colorado

Publications Chair
Kevin Skadron, Univ. of Virginia

Steering Committee
Richard Belgard, Consultant

Tom Conte, NC State
Kemal Ebcioglu, IBM
Matt Farrens, UC-Davis
Wen-mei Hwu, Univ. of Illinois
Yale Patt, UT-Austin
Ronny Ronen, Intel Israel
Mike Schlansker, HP Labs
Andy Wolfe, SONICblue

Program Committee
Saman Amarasinghe, MIT
Krste Asanovic, MIT
David Bernstein, IBM Israel
Geoff Brown, Ironbridge
Francky Catthoor, IMEC
Bob Colwell, Intel
Tom Conte, NCSU
Henk Corporaal, TU Delft
Kemal Ebcioglu, IBM
Antonio Gonzalez, UPC
Jim Goodman, U.Wisconsin/Intel
Thomas Gross, ETH
Rajiv Gupta, U.Arizona
Wen-Mei Hwu, UIUC
David Kaeli, Northeastern
Steve Keckler, U.Texas Austin
Geoff Lowney, Compaq
Bill Mangione-Smith, UCLA
Hans Mulder, Intel
Walid Najjar, UCRiverside
CJ Newburn, Intel
Bob Rau, HP Labs
Andre Seznec, IRISA/INRIA
Carol Thompson, HP
Nigel Topham, Siroyan
Mateo Valero, UPC
Andy Wolfe, SONICblue
Donald Yeung, U.Maryland
Cliff Young, Lucent Bell Labs


micro logo


December 1-5 2001

Marriott Hotel, Austin, Texas



Sponsored by IEEE TC-MARCH ieee logo and ACM SIGMICROacm logo

The 34th International Symposium on Microarchitecture is the premiere forum for discussing new techniques to extract high levels of instruction-level parallelism via hardware and software. The goals of this symposium are to bring together researchers in fields related to microarchitecture and instruction-level parallelism, to encourage technical interaction, and to advance the state of the art of high-performance microarchitectures and fine-grain parallel processing. Papers are solicited in fields including the following:

  • ILP architectures and designs: superscalar, VLIW, multithreaded, ...
  • Compiler techniques for instruction-level parallelism
  • Architectures and compilers for embedded processors, DSPs (imaging, graphics, low power, etc.)
  • Dynamic optimization, emulation, and object code translation
  • Advanced software and hardware speculation and prediction schemes
  • Hardware/compiler techniques for improving memory system performance
  • Hardware/software techniques for efficient systems on a single chip
  • Hardware/software techniques for fine-grain parallel processing
  • THE DEADLINE FOR SUBMISSIONS IS JUNE 15th, 2001 There is an automatic, one week extension for late papers. There will be no other extensions. Submit one electronic copy of the paper in postscript or PDF format. Please visit the website for paper format guidelines and submission instructions. In order to guarantee the success of your electronic submissions please make sure that your postscript submission can be previewed via the ghostview tool. Notification of acceptance will occur by August 13, 2001.