Championship Value Prediction Leaderboard




8KB Storage Budget

Rank
IPC (public traces)
Speedup
Contestant(s)
Paper Files Submitted
1
3.433
+23.5%
André Seznec (IRISA/INRIA) Exploring Value Prediction with the EVES predictor .tar.gz June 2018
2
3.211
+15.5%
Yasuo Ishii (Arm) Context-Base Computational Value Predictor with Value Compression .tar.gz June 2018
3
2.874
+3.4%
Kenichi Koizumi, Kei Hiraki and Mary Inaba (The University of Tokyo, Japan) H3VP: History-based High-reliable Hybrid Value Predictor .tar.gz June 2018
-
2.779
+0%
CVP Baseline June 2018

Perfect Value Prediction achieves 5.755 IPC (+107.0%).


32KB Storage Budget

Rank
IPC (public traces)
Speedup
Contestant(s)
Paper Files Submitted
1
3.573
+28.6%
André Seznec (IRISA/INRIA) Exploring Value Prediction with the EVES predictor .tar.gz June 2018
2
2.898
+4.3%
Kenichi Koizumi, Kei Hiraki and Mary Inaba (The University of Tokyo, Japan) H3VP: History-based High-reliable Hybrid Value Predictor .tar.gz June 2018
-
2.779
+0%
CVP Baseline June 2018

Perfect Value Prediction achieves 5.755 IPC (+107.0%).


Unlimited Storage Budget

Rank
IPC (public traces)
Speedup
Contestant(s)
Paper Files Submitted
1
3.773
+35.8%
André Seznec (IRISA/INRIA) Exploring Value Prediction with the EVES predictor .tar.gz June 2018
2
3.491
+25.6%
Nayan Deshmukh, Snehil Verma, Prakhar Agrawal, Biswabandan Panda, Mainak Chaudhuri (Indian Institute of Technology Kanpur) DFCM++: Augmenting DFCM with Early Update and Data Dependency-driven Value Estimation .tar.gz June 2018
3
3.056
+10.0%
Kenichi Koizumi, Kei Hiraki and Mary Inaba (The University of Tokyo, Japan) H3VP: History-based High-reliable Hybrid Value Predictor .tar.gz June 2018
-
2.779
+0%
CVP Baseline June 2018

Perfect Value Prediction achieves 5.755 IPC (+107.0%). Predictor provided in the kit achieves 3.050 IPC (+9.7%).


CVPv6 Configuration Used for Ranking

VP_ENABLE = 1
VP_PERFECT = 0
WINDOW_SIZE = 256
FETCH_WIDTH = 16
FETCH_NUM_BRANCH = 0
FETCH_STOP_AT_INDIRECT = 0
FETCH_STOP_AT_TAKEN = 0
FETCH_MODEL_ICACHE = 0
PERFECT_BRANCH_PRED = 0
PERFECT_INDIRECT_PRED = 0
PIPELINE_FILL_LATENCY = 5
NUM_LDST_LANES = 0 (unbounded)
NUM_ALU_LANES = 0 (unbounded)
MEMORY HIERARCHY CONFIGURATION---------------------
PERFECT_CACHE = 0
WRITE_ALLOCATE = 1
Within-pipeline factors:
AGEN latency = 1 cycle
Store Queue (SQ): SQ size = window size, oracle memory disambiguation, store-load forwarding = 1 cycle after store's or load's agen.
* Note: A store searches the L1$ at commit. The store is released
* from the SQ and window, whether it hits or misses. Store misses
* are buffered until the block is allocated and the store is
* performed in the L1$. While buffered, conflicting loads get
* the store's data as they would from the SQ.
L1$: 32 KB, 4-way set-assoc., 64B block size, 2-cycle search latency
L2$: 1 MB, 8-way set-assoc., 64B block size, 12-cycle search latency
L3$: 8 MB, 16-way set-assoc., 128B block size, 60-cycle search latency
Main Memory: 150-cycle fixed search time