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Annual IEEE/ACM International Symposium on Microarchitecture

MICRO Test of Time Award

The MICRO Test of Time (ToT) award recognizes the most influential papers published in prior sessions of the International Symposium on Microarchitecture, each of whom have had significant impact in the field.

Every year, papers are nominated for the award, either by recommendation from members of the computer architecture community, or automatically if they meet a minimum citation count criterion. Winning papers are selected by the ToT Award Committee, and are announced at that year's MICRO conference.

Award Committee
Rich Belgard
Pradip Bose
Bill Mangione-Smith
Onur Mutlu, chair
Andre Seznec
Uri Weiser

2017 Paper Nominations

Nominations are now open for the 2017 award, and are due on July 15, 2017. Please read the call for nominations to see how you can nominate a paper.

Past ToT Award Winners


The following paper was awarded the third MICRO Test of Time Award in 2016. This paper was selected from among all the 156 papers published in MICRO conferences that were held between 1994 and 1998 (inclusive).

ConferencePaper TitleAuthors
MICRO 1994 Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops B. Ramakrishna Rau


The following paper was awarded the second MICRO Test of Time Award in 2015. This paper was selected from among all the 156 papers published in MICRO conferences that were held between 1993 and 1997 (inclusive).

ConferencePaper TitleAuthors
MICRO 1996 Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching Eric Rotenberg, Steve Bennett, James E. Smith

Related Documents

2015 Call for Nominations


The following are the 10 papers that were awarded the first MICRO Test of Time Award in 2014. These 10 papers were selected from among all the 544 papers published in MICRO conferences that were held between 1968 and 1992 (inclusive).

ConferencePaper TitleAuthors
MICRO 1978 Microprogrammed Implementation of A Single Chip Microprocessor Skip Stritter, Nick Tredennick
MICRO 1981 Some Scheduling Techniques and An Easily Schedulable Horizontal Architecture for High Performance Scientific Computing B. Ramakrishna Rau, C. D. Glaeser
MICRO 1982 MIPS: A Microprocessor Architecture John Hennessy, Norman Jouppi, Steven Przybylski, Christopher Rowen, Thomas Gross, Forest Baskett, John Gill
MICRO 1985 Critical Issues Regarding HPS, A High Performance Microarchitecture Yale N. Patt, Stephen W. Melvin, Wen-mei Hwu, Michael C. Shebanow
MICRO 1985 HPS, A New Microarchitecture: Rationale and Introduction Yale N. Patt, Wen-mei Hwu, Michael Shebanow
MICRO 1988 Hardware Support for Large Atomic Units in Dynamically Scheduled Machines Stephen W. Melvin, Michael C. Shebanow, Yale N. Patt
MICRO 1991 Two-Level Adaptive Training Branch Prediction Tse-Yu Yeh, Yale N. Patt
MICRO 1992 Effective Compiler Support For Predicated Execution Using the Hyperblock Scott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, Roger A. Bringmann
MICRO 1992 Code Generation Schema for Modulo Scheduled Loops B. Ramakrishna Rau, Michael S. Schlansker, P. P. Tirumalai
MICRO 1992 Executing Compressed Programs on An Embedded RISC Architecture Andrew Wolfe, Alex Chanin

Related Documents

2014 Call for Nominations (PDF)

Onur Mutlu, Rich Belgard, Nick Tredennick, Mike Schlansker
The 2014 MICRO Test of Time Award Winners: From 1978 to 1992
IEEE Micro, Vol. 36, No. 1, January/February 2016

Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor
IEEE Micro, Vol. 36, No. 4, July/August 2016