43rd International Symposium on
Microarchitecture

Sunday, December 5th, 2010

4:00-8:00pm: Registration (Grand Ballroom Foyer)

6:00-8:00pm: Reception (Salons 1, 2, & 3)

Monday, December 6th, 2010

7:00-4:00pm: Registration (Grand Ballroom Foyer)

8:00-9:15am: Welcome and Keynote #1 (pdf) (Grand Ballroom)
Krisztian Flautner, VP of Research and Development, ARM

9:15-9:45am: Break

9:45-11:45am: Session 1: Transactional Systems (Grand Ballroom)
Session Chair: Scott Mahlke, University of Michigan, Ann Arbor

Scalable Speculative Parallelization on Commodity Clusters
Hanjun Kim, Arun Raman, Feng Liu (Princeton University), Jae W. Lee (Parakinetics), David I. August (Princeton University)

Hardware Support for Relaxed Concurrency Control in Transactional memory Systems
Utku Aydonat, Tarek Abdelrahman (University of Toronto)

A Dynamically Adaptable Hardware Transactional Memory"
Marc Lupon (UPC), Grigorios Magklis, Antonio Gonzalez (Intel and UPC)

ASF: AMD64 Extension for Lock-free Data Structures and Transactional Memory
Jaewoong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth (AMD), Dan Grossman (University of Washington), David Christie (AMD)


11:45-1:00pm: Lunch

1:00-3:00pm: Session 2A: Scheduling (Salons 1,2,3)
Session Chair: Tor Aamodt, University of British Columbia

Memory Latency Reduction via Thread Throttling
Hsiang-Yun Cheng, Chung-Hsiang Lin (National Taiwan University), Jian Li (IBM Austin Research Laboratory), Chia-Lin Yang (National Taiwan University)

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter (Carnegie Mellon University)

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-guided Thread Scheduling
Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks (Harvard University)

Task Superscalar: An Out-of-Order Task Pipeline
Yoav Etsion, Felipe Cabarcas, Alejandro Rico (BSC), Alex Ramirez (BSC and UPC), Rosa M. Badia (BSC), Eduard Ayguade (BSC and UPC), Jesus Labarta (BSC and UPC), Mateo Valero (BSC and UPC)


1:00-3:00pm: Session 2B: Reliability/Scheduling (Salons 4,5,6)
Session Chair: Rakesh Kumar, University of Illinois at Urbana-Champaign

Combating Aging with the Colt Duty Cycle Equalizer
Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko Lipasti (University of Wisconsin)

SAFER: Stuck-At-Fault Error Recovery for Memories
Nak Hee Seong, Dong Hyuk Woo (Georgia Institute of Technology), Vijayalakshmi Srinivasan, Jude A. Rivers (IBM Research), Hsien-Hsin S. Lee (Georgia Institute of Technology)

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-case Vulnerability to Soft Errors
Arun Arvind Nair, Lizy Kurian John (University of Texas at Austin), Lieven Eeckhout (Ghent University)

Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
Daniel Y Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh (Cornell University)


3:00-3:30pm: Break

3:30-5:30pm: Session 3A: Caching (Salons 1,2,3)
Session Chair: Vijayalakshmi Srinivasan, IBM Research

Achieving Non-Inclusive Cache Performance with Inclusive Caches
Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon Steely Jr., Joel Emer (Intel)

Spatiotemporal Management of Capacity for Intra-Core Last Level Caches
Dongyuan Zhan, Hong Jiang, Sharad C. Seth (University of Nebraska – Lincoln)

Sampling Dead Block Prediction for Last-Level Caches
Samira M. Khan, Yingying Tian (The University of Texas at San Antonio), Daniel A. Jimenez (The University of Texas at San Antonio / Barcelona Supercomputing Center)

The ZCache: Decoupling Ways and Associativity
Daniel Sanchez, Christos Kozyrakis (Stanford University)


3:30-5:30pm: Session 3B: Data Parallelism (Salons 4,5,6)
Session Chair: John Kim, KAIST

Efficient Selection of Vector Instructions using Dynamic Programming
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar (Rice University)

Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard Vuduc (Georgia Institute of Technology)

Single-chip Heterogeneous Computing: Does the future include Custom Logic, FPGAs, and GPUs?
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai (Carnegie Mellon University)

Dynamic Thread Creation for Improving Processor Utilization on SIMT Streaming Processor Architectures
Michael Steffen, Joseph Zambreno (Iowa State University)


9:00pm: Business Meeting (Conference A)


Tuesday, December 7th, 2010

7:30-4:00pm: Registration (Grand Ballroom Foyer)

8:30-9:30am: Keynote #2 (Grand Ballroom)
Gary Lauterbach, CTO and Co-Founder, SeaMicro

9:30-10:00am: Break

10:00-12:00pm Session 4A: Concurrency (Salons 1,2,3)
Session Chair: Sanjay Patel, University of Illinois at Urbana-Champaign

InstantCheck: Checking the Determinism of Parallel Programs Using On-the-fly Incremental Hashing
Adrian Nistor, Darko Marinov, Josep Torrellas (University of Illinois at Urbana-Champaign)

Tolerating Concurrency Bugs Using Transactions as Lifeguards
Jie Yu, Satish Narayanasamy (University of Michigan)

Architectural support for Fair Reader-Writer Locking
Enrique Vallejo, Ramón Beivide (University of Cantabria), Adrián Cristal (Barcelona Supercomputing Center), Tim Harris (Microsoft Research Cambridge), Fernando Vallejo (University of Cantabria), Osman Unsal (Barcelona Supercomputing Center), Mateo Valero (Barcelona Supercomputing Center and UPC)

AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection
Abdullah Muzahid (University Of Illinois at Urbana-Champaign), Norimasa Otsuki (Renesas Electronics Corp), Josep Torrellas (University Of Illinois at Urbana-Champaign)


10:00-12:00pm Session 4B: Microarchitecture I (Salons 4,5,6)
Session Chair: Huiyang Zhou, North Carolina State University

Register Cache System not for Latency Reduction Purpose
Ryota Shioya (University of Tokyo), Kazuo Horio (Fujitsu Laboratories Ltd.), Masahiro Goshima, Shuichi Sakai (University of Tokyo)

Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors
Shekhar Srikantaiah, Mahmut Kandemir (The Pennsylvania State University)

Erasing Core Boundaries for Robust and Configurable Performance
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott Mahlke (University of Michigan)

Minimal Multi-Threading: Finding and Removing Redundant Instructions in Multi-Threaded Processors
Guoping Long (Institute of Computing Technology, Chinese Academy of Sciences), Diana Franklin, Susmit Biswas, Pablo Ortiz (Universit of California, Santa Barbara), Jason Oberg (University of California, San Diego), Dongrui Fan (Institute of Computing Technology, Chinese Academy of Sciences), Frederic T. Chong (University of California, Santa Barbara)


12:00-1:30pm: Lunch

1:30-3:30pm Session 5A: Memories (Salons 1,2,3)
Session Chair: Hsien-Hsin Lee, Georgia Institute of Technology

Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
Timothy Miller, James Dinan, Renji Thomas, Bruce Adcock, Radu Teodorescu (The Ohio State University)

Understanding the Energy Consumption of Dynamic Random Access Memories
Thomas Vogelsang (Rambus Inc.)

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
Jeffrey Stuecheli (University of Texas Austin/IBM Austin), Dimitris Kaseridis (University of Texas Austin), Hillery Hunter (IBM Watson), Lizy John (University of Texas Austin)

Moneta: A High-performance Storage Array Architecture for Next-generation, Non-volatile Memories
Adrian Caulfield, Arup De, Joel Coburn, Todor Mollov, Rajesh Gupta, Steven Swanson (University of California, San Diego)


1:30-3:30pm Session 5B: NoCs (Salons 4,5,6)
Session Chair: Sudhakar Yalamanchili, Georgia Institute of Technology

Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
Minseon Ahn, Eun Jung Kim (Texas A&M University)

LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support
Jin Ouyang, Yuan Xie (The Pennsylvania State University)

Throughput-Effective On-Chip Networks for Manycore Accelerators
Ali Bakhoda (University of British Columbia), John Kim (KAIST), Tor M. Aamodt (University of British Columbia)

Adaptive Flow Control for Robust Performance and Energy
Syed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi, T. N. Vijaykumar (Purdue University)


3:30-4:00pm: Break

4:30-4:45pm: Departure to the Georgia Aquarium

5:00-10:00pm: Excursion at the Georgia Aquarium


Wednesday, December 8th, 2010

7:30-12:00pm: Registration (Grand Ballroom Foyer)

8:30-10:00am: Session 6A: Coherence (Salons 1,2,3)
Session Chair: Andreas Moshovos, University of Toronto

ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
Xuehai Qian, Wonsun Ahn, Josep Torrellas (University of Illinois, Urbana-Champaign)

Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
Daehoon Kim, Hwanju Kim, Jaehyuk Huh (KAIST)

Fractal Coherence: Scalably Verifiable Cache Coherence
Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin (Duke University)


8:30-10:00am: Session 6B: Microarchitecture II (Salons 4,5,6)
Session Chair: Hyesoon Kim, Georgia Institute of Technology

A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Christophe Dubach, Timothy M. Jones (University of Edinburgh), Edwin V. Bonilla (Australian National University), Michael F.P. O'Boyle (University of Edinburgh)

ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
Matthew A. Watkins, David H. Albonesi (Cornell University)

Probabilistic Distance-based Arbitration: Providing Equality of Service for Many-core CMPs
Michael Lee, John Kim (KAIST), Dennis Abts, Mike Marty (Google), Jae Lee (Parakinetics)


10:00-10:30am: Break

10:30-12:00pm Session 7: Tools (Grand Ballroom)
Session Chair: Milos Prvulovic, Georgia Institute of Technology

Adaptive and Speculative Slack Simulations of CMPs on CMPs
Jianwei Chen (ORACLE), Lakshmi Kumar Dabbiru, Daniel Wong, Murali Annavaram, Michel Dubois (University Of Southern California)

SD3: A Scalable Approach to Dynamic Data-Dependence Profiling
Minjang Kim, Hyesoon Kim (Georgia Tech), Chi-Keung Luk (Intel Corporation)

Automatic Parallelization in a Binary Rewriter
Aparna Kotha, Kapil Anand, Mathew Smithson, Greeshma Yellareddy, Rajeev Barua (University of Maryland, College Park)


12:00pm- Closing