42nd International Symposium on
Microarchitecture Sunday, December 13, 2009
10:00-10:25: Characterizing and Mitigating the Impact of Process Variations on Phase Change based Memory Systems Wangyuan Zhang, University of Florida Tao Li, University of Florida 10:25-10:50: Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling Moinuddin K. Qureshi, IBM Research John Karidis, IBM Research Vijayalakshmi Srinivasan, IBM Research Michele Franceschini, IBM Research Luis Lastras, IBM Research Bulent Abali, IBM Research 10:50-11:15: Characterizing Flash Memory: Anomalies, Observations, and Applications Laura M.Grupp, University of California, San Diego Adrian M. Caulfield, University of California, San Diego Joel Coburn, University of California, San Diego Steven Swanson, University of California, San Diego Eitan Yaakobi, University of California, San Diego Paul H. Siegel, University of California, San Diego Jack K. Wolf, University of California, San Diego 11:15-11:40: Complexity Effective Memory Access Scheduling for Many-Core Accelerator Architectures George L. Yuan, University of British Columbia Ali Bakhoda, University of British Columbia Tor M. Aamodt, University of British Columbia 11:45-1:15pm: Lunch
1:15-1:40: Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping Chi-Keung Luk, Intel Sunpyo Hong, Georgia Tech Hyesoon Kim, Georgia Tech 1:40-2:05: DDT: Design and Evaluation of a Dynamic Program Analysis for Optimizing Data Structure Usage Changhee Jung, Georgia Institute of Technology Nathan Clark, Georgia Institute of Technology 2:05-2:30: Tree Register Allocation Hongbo Rong, Microsoft 2:30-2:55: Portable Compiler Optimization Across Embedded Programs and Microarchitectures using Machine Learning Christophe Dubach, University of Edinburgh Timothy M. Jones, University of Edinburgh Edwin V. Bonilla, University of Edinburgh Grigori Fursin, INRIA Saclay, France Michael F.P. O'Boyle, University of Edinburgh
1:15-1:40: Improving Cache Lifetime Reliability at Ultra-low Voltages Zeshan Chishti, Intel Alaa R. Alameldeen, Intel Chris Wilkerson, Intel Wei Wu, Intel Shih-Lien Lu, Intel 1:40-2:05: ZerehCache: Armoring Cache Architectures in High Defect Density Technologies Amin Ansari, University of Michigan, Ann Arbor Shantanu Gupta, University of Michigan, Ann Arbor Shuguang Feng, University of Michigan, Ann Arbor Scott Mahlke, University of Michigan, Ann Arbor 1:05-2:30: Low Vccmin Fault-Tolerant Cache with Highly Predictable Performance Jaume Abellà, Intel Barcelona Research Center Javier Carretero, Intel Barcelona Research Center Pedro Chaparro, Intel Barcelona Research Center Xavier Vera, Intel Barcelona Research Center Antonio González, Intel Barcelona Research Center; Universitat Politècnica de Catalunya 2:30-2:55: mSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems Siva Kumar Sastry Hari, University of Illinois, Urbana-Champaign Man-Lap Li, University of Illinois, Urbana-Champaign Pradeep Ramachandran, University of Illinois, Urbana-Champaign Byn Choi, University of Illinois, Urbana-Champaign Sarita V. Adve, University of Illinois, Urbana-Champaign 2:55-3:15pm: Break
3:15-3:40: BulkCompiler: High-Performance Sequential Consistency through Cooperative Compiler and Hardware Support Wonsun Ahn, University of Illinois, Urbana-Champaign Shanxiang Qi, University of Illinois, Urbana-Champaign Marios Nicolaides, University of Illinois, Urbana-Champaign Josep Torrellas, University of Illinois, Urbana-Champaign Jae-Woo Lee, Purdue University Xing Fang, Purdue University Samuel Midkiff, Purdue University David Wong, Intel 3:40-4:05: EazyHTM: Eager-Lazy Hardware Transactional Memory Saša Tomić, Barcelona Supercomputing Center; Universitat Politècnica de Catalunya Cristian Perfumo, Barcelona Supercomputing Center; Universitat Politècnica de Catalunya Chinmay Kulkarni, Barcelona Supercomputing Center; BITS Pilani Adrià Armejach, Barcelona Supercomputing Center; Universitat Politècnica de Catalunya Adrián Cristal, Barcelona Supercomputing Center Osman Unsal, Barcelona Supercomputing Center Tim Harris, Microsoft Research Cambridge Mateo Valero, Barcelona Supercomputing Center 4:05-4:30: Proactive Transaction Scheduling for Contention Management Geoffrey Blake, University of Michigan, Ann Arbor Ronald G. Dreslinski, University of Michigan, Ann Arbor Trevor Mudge, University of Michigan, Ann Arbor
3:15-3:40: Into the Wild: Studying Real User Activity Patterns to Guide Power Optimization for Mobile Architectures Alex Shye, Northwestern University Benjamin Scholbrock, Northwestern University Gokhan Memik, Northwestern University 3:40-4:05: A Microarchitecture-based Framework for Pre- and Post-Silicon Power Delivery Analysis Mahesh Ketkar, Intel Eli Chiprout, Intel 4:05-4:30: Reducing Peak Power with a Table-Driven Adaptive Processor Core Vasileios Kontorinis, University of California, San Diego Amirali Shayan, University of California, San Diego Rakesh Kumar, University of Illinois, Urbana-Champaign Dean Tullsen, University of California, San Diego 4:30-5pm: Break
5:00-5:25: Extending the Effectiveness of 3D-Stacked DRAM Caches with an Adaptive Multi-Queue Policy Gabriel H. Loh, Georgia Institute of Technology 5:25-5:50: An Hybrid eDRAM/SRAM Macrocell to Implement First-level Data Caches Alejandro Valero, Universidad Politécnica de Valencia Julio Sahuquillo, Universidad Politécnica de Valencia Salvador Petit, Universidad Politécnica de Valencia Vicente Lorente, Universidad Politécnica de Valencia Ramón Canal, Universitat Politècnica de Catalunya Pedro López, Universidad Politécnica de Valencia José Duato, Universidad Politécnica de Valencia 5:50-6:15: Variation-Tolerant Non-Uniform 3D Cache Management in Die Stacked Multicore Processor Bo Zhao, University of Pittsburgh Yu Du, University of Pittsburgh Youtao Zhang, University of Pittsburgh Jun Yang, University of Pittsburgh
5:00-5:25: In-Network Coherence Filtering: Snoopy Coherence without Broadcasts Niket Agarwal, Princeton University Li-Shiuan Peh, Princeton University Niraj K. Jha, Princeton University 5:25-5:50: SCARAB: A Single Cycle Adaptive Routing and Bufferless Network Mitchell Hayenga, University of Wisconsin, Madison Natalie Enright-Jerger, University of Toronto Mikko Lipasti, University of Wisconsin, Madison 5:50-6:15: Low-Cost Router Microarchitecture for On-Chip Networks John Kim, KAIST
Tuesday, December 15, 2009
10:00-10:25: Preemptive Virtual Clock: A Flexible, Efficient and Cost-effective QOS Scheme for Networks-on-Chip Boris Grot, University of Texas, Austin Stephen W. Keckler, University of Texas, Austin Onur Mutlu, Carnegie Mellon University 10:25-10:50: Application-Aware Prioritization Mechanisms for On- Chip Networks Reetuparna Das, Pennsylania State University Onur Mutlu, Carnegie Mellon University Thomas Moscibroda, Microsoft Research Chita R. Das, Pennsylania State University 10:50-11:15: A Case for Dynamic Frequency Tuning in On-Chip Networks Asit K. Mishra, Pennsylvania State University Reetuparna Das, Pennsylvania State University Soumya Eachempati, Pennsylvania State University Ravi Iyer, Intel N. Vijaykrishnan, Pennsylvania State University Chita R. Das, Pennsylvania State University 11:15-11:40: Light Speed Arbitration and Flow Control for Nanophotonic Interconnects Dana Vantrease, University of Wisconsin, Madison Nathan Binkert, HP Labs Robert Schreiber, HP Labs Mikko Lipasti, University of Wisconsin, Madison 11:45am-1:15pm: Lunch
1:15-1:40: Coordinated Control of Multiple Prefetchers in Multi-Core Systems Eiman Ebrahimi, University of Texas, Austin Onur Mutlu, Carnegie Mellon University Chang Joo Lee, University of Texas, Austin Yale N. Patt, University of Texas, Austin 1:40-2:05: Improving Memory Bank-Level Parallelism in the Presence of Prefetching Chang Joo Lee, University of Texas, Austin Veynu Narasiman, University of Texas, Austin Onur Mutlu, Carnegie Mellon University Yale N. Patt, University of Texas, Austin 2:05-2:30: ESKIMO - Energy Savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem Ciji Isen, University of Texas, Austin Lizy John, University of Texas, Austin 2:30-2:55: Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance Sangyeun Cho, University of Pittsburgh Hyunjin Lee, University of Pittsburgh
1:15-1:40: Using a Configurable Processor Generator for Computer Architecture Prototyping Alex Solomatnikov, Hicamp Systems Inc. Amin Firoozshahian, Hicamp Systems Inc. Ofer Shacham, Stanford University Zain Asgar, Stanford University Megan Wachs, Stanford University Wajahat Qadeer, Stanford University Stephen Richardson, Stanford University Mark Horowitz, Stanford University 1:40-2:05: Polymorphic Pipeline Array: A Flexible Multicore Accelerator with Virtualized Execution for Mobile Multimedia Applications Hyunchul Park, University of Michigan, Ann Arbor Yongjun Park, University of Michigan, Ann Arbor Scott Mahlke, University of Michigan, Ann Arbor 2:05-2:30: Ordering Decoupled Metadata Accesses in Multiprocessors Hari Kannan, Stanford University 2:30-2:55: Control Flow Obfuscation with Information Flow Tracking Haibo Chen, Fudan University Liwei Yuan, Fudan University Xi Wu, Fudan University Binyu Zang, Fudan University Bo Huang, Intel Pen-chung Yew, University of Minnesota 2:55-3:15pm: Break
3:15-3:40: Pseudo-LIFO: The Foundation of a New Family of Replacement Policies for Last-level Caches Mainak Chaudhuri, Indian Institute of Technology, Kanpur 3:40-4:05: Comparing Cache Architectures and Coherency Protocols on x86-64 Multicore SMP Systems Daniel Hackenberg, ZIH, TU Dresden Daniel Molka, ZIH, TU Dresden Wolfgang E. Nagel, ZIH, TU Dresden 4:05-4:30: A Tagless Coherence Directory Jason Zebchuk, University of Toronto Vijayalakshmi Srinivasan, IBM Moinuddin K. Qureshi, IBM Andreas Moshovos, University of Toronto
3:15-3:40: Tribeca: Design for PVT Variations with Local Recovery and Fine-grained Adaptation Meeta Sharma Gupta, Harvard University Jude A. Rivers, IBM Pradip Bose, IBM Gu-Yeon Wei, Harvard University David Brooks, Harvard University 3:40-4:05: The BubbleWrap Many-core: Popping Cores for Sequential Acceleration Ulya R. Karpuzcu, University of Illinois, Urbana-Champaign Brian Greskamp, University of Illinois, Urbana-Champaign Josep Torrellas, University of Illinois, Urbana-Champaign 4:05-4:30: Multiple Clock and Voltage Domains for Chip Multi Processors Efraim Rotem, Intel Ran Ginosar, Technion Avi Mendelson, Microsoft Uri Weiser, Technion 4:30-4:45pm: Break
Wednesday, December 16, 2009
8:45-9:10: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Sheng Li, University of Notre Dame Jung Ho Ahn, HP Labs Richard D. Strong, University of California, San Diego Jay B. Brockman, University of Notre Dame Dean M. Tullsen, University of California, San Diego Norman P. Jouppi, HP Labs 9:10-9:35: Characterizing the Resource-Sharing Levels in the UltraSPARC T2 Processor Vladimir Čakarević, Barcelona Supercomputing Center Petar Radojković, Barcelona Supercomputing Center Javier Verdú, Universitat Politècnica de Catalunya Alex Pajuelo, Universitat Politècnica de Catalunya Francisco J. Cazorla, Barcelona Supercomputing Center Mario Nemirovsky, Barcelona Supercomputing Center, ICREA Mateo Valero, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya 9:35-10:00: Execution Leases: A Hardware-Supported Mechanism for Enforcing Strong Non-Interference Mohit Tiwari, University of California, Santa Barbara Xun Li, University of California, Santa Barbara Hassan M G Wassel, University of California, Santa Barbara Frederic T. Chong, University of California, Santa Barbara Timothy Sherwood, University of California, Santa Barbara
8:45-9:10: Optimizing Shared Cache Behavior of Chip Multiprocessors Mahmut Kandemir, Pennsylvania State University Sai Prasanth Muralidhara, Pennsylvania State University Sri Hari Krishna Narayanan, Pennsylvania State University Yuanrui Zhang, Pennsylvania State University Ozcan Ozturk, Bilkent University 9:10-9:35: SHARP Control: Controlled Shared Cache Management in Chip Multiprocessors Shekhar Srikantaiah, Pennsylvania State University Mahmut Kandemir, Pennsylvania State University Qian Wang, Pennsylvania State University 9:35-10:00: Adaptive Line Placement with the Set Balancing Cache Dyer Rolan, Universidade da Coruña Basilio B. Fraguela, Universidade da Coruña Ramón Doallo, Universidade da Coruña 10:00-10:20am: Break
10:20-10:45: Light64: Lightweight Hardware Support for Race Detection during Systematic Testing of Parallel Programs Adrian Nistor, University of Illinois, Urbana-Champaign Darko Marinov, University of Illinois, Urbana-Champaign Josep Torrellas, University of Illinois, Urbana-Champaign 10:45-11:10: Finding Concurrency Bugs with Context-Aware Communication Graphs Brandon Lucia, University of Washington Luis Ceze, University of Washington 11:10-11:35: Offline Symbolic Analysis for Multi-Processor Execution Replay Dongyoon Lee, University of Michigan, Ann Arbor Mahmoud Said, Western Michigan University Satish Narayanasamy, University of Michigan, Ann Arbor Zijiang (James) Yang, Western Michigan University Cristiano Pereira, Intel 11:35-12:00: Architecting a Chunk-based Memory Race Recorder in Modern CMPs Gilles Pokam, Intel Cristiano Pereira, Intel Klaus Danne, Intel Rolf Kassa, Intel Ali-Reza Adl-Tabatabai, Intel 12:00-12:15pm: Break
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