T2. On-Chip Communication Architectures: Busses, Networks-on-Chip and Beyond Organizers: Nikil Dutt, Luca Benini, and Sudeep Pasricha, University of California at Irvine and University of Bologna
T4. VLIW Compilation Environment and Multi-Processor Architecture of Diopsis, the RISC + floating-Point VLIW DSP System-On-Chip Designed for High Quality Acoustic Applications Organizers: Gert Goossens, Pier Stanislao and Piergiovanni Bazzana, ATMEL Roma and TARGET Compiler Technologies