Abstract: Many new applications are written in languages such as Java and C# that have managed runtime environments. The different needs and performance characteristics of such applications affect how hardware resources are used in general and how transactional memory can best be implemented in particular. This tutorial will survey hardware and software transactional memory implementation techniques with an emphasis on (1) what is easier in a managed runtime environment, (2) what is harder in a managed runtime environment, and (3) how transactions interact with other runtime services such as garbage collection and dynamic compilation.
The tutorial will also present the programmers' view of transactions, which is essential if transactions will succeed at making shared-memory concurrent programming easier. We will discuss the motivation, semantics, and design of software transactions in a managed language. Our motivation takes the novel view that transactions can improve concurrency much like garbage collection can improve memory management. We will describe the semantics of transactions and how they interact with existing language constructs such as exceptions. We will also introduce the semantics of isolation, ordering, conflict detection, and nested transactions.
On the implementation side, we will discuss both software and hardware transactional memories (STMs and HTMs, respectively). On the software side, we will survey a number of STM implementations for managed runtimes, and we will discuss differences between managed runtimes and native environments. On the hardware side, we will discuss the three approaches for hardware-support of transactional memory: pure HTMs, hybrid approaches that use HTMs in conjunction with STMs, and hardware acceleration for STMs. We will overview the industrial HTM implementations in Azul Systems's Vega and Sun's Rock processors. We will also describe alternative applications of this hardware including software lock elision and speculative compiler optimizations.
We will then use a case study to delve into the workload characteristics when run under an STM. The case study will be based on workloads and a runtime developed using the Apache Harmony Environment and the High Performance McRT (Multicore Runtime) STM. Apache Harmony (http://harmony.apache.org) is the open source Java SE implementation done under Apache License v2. McRT STM is a high performance runtime environment. The workloads we will characterize and demonstrate include simple microbenchmarks as well as large multithreaded Java applications. We will also sketch the work being done in native C/C++workloads.
We will conclude the tutorial with open research problems in this field and present pointers to implementations that are available for researchers to continue to make progress in this field.
Suresh Srinivas is a Principal Engineer in the Software Solutions Group within Intel Corporation where he is currently focused on new technology development using open source technologies. He has 15 years of experience developing language runtimes, tools, and compilers. During his career he has published over 15+ peer reviewed articles and has 7 patents pending. Prior to Intel he was at SGI leading their JVM efforts. He obtained his PhD in Computer Science from Indiana University specializing in tools and runtimes for parallel languages. While not working you can find him volunteering, cooking or hiking in the beautiful Pacific Northwest.
Vijay Menon is a senior research scientist in the Programming Systems Lab at Intel investigating new programming technologies for multi-core systems. His primary areas of research include compilers, managed runtimes, and transactional memory. Vijay holds a Ph.D. in Computer Science from Cornell University and a B.S. in Electrical Engineering and Computer Science from the University of California at Berkeley.
Dan Grossman joined the faculty of the Department of Computer Science & Engineering at the University of Washington in 2003 after completing his Ph.D. at Cornell University. His research focus is programming-language design and implementation, particularly for reliable low-level and concurrent software. He has received an NSF CAREER award. He is best known as a primary designer and implementor of the Cyclone programming language, which is a memory-safe dialect of C, and for his research on the design and semantics of transactions for programming languages. Dan has been elected by his department's undergraduates for their "Teacher of the Year" award.
Craig Zilles is an Assistant Professor in the Computer Science department at the University of Illinois at Urbana-Champaign. His current research focuses on the interaction between compilers and computer architecture, especially in the context of managed and dynamic languages. He received his Ph.D. in 2002 from Wisconsin- Madison for his work with Guri Sohi on Speculative Slices and Master/ Slave Speculative Parallelization. Prior to his work on computer architecture, he developed the first algorithm that allowed rendering arbitrary three-dimensional polygonal shapes for haptic interfaces (force-feedback human-computer interfaces). He holds 5 patents and has received both an NSF CAREER award and the College of Engineering's Rose Award for Teaching Excellence.
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