Title: Tutorial on Microprocessor Memory Array Circuits for Architects

Steven Hsu (Intel)
Dinesh Somasekhar (Intel)
Shih-Lien Lu (Intel)

Abstract: More and more devices on a modern microprocessor are devoted to memory arrays. For example, even the first generation Pentium(tm) devoted more than 50% of the 3 million+ transistors for implementing cache, table, register files, etc. However, these memory arrays are quite different in circuit topology and have different characteristics due to their requirements. Some are based on differential small signals, while others are single ended full swing. With technology advancement designing these arrays is challenged with many constraints. This tutorial intends to extract out general technology trends and circuit design challenges for microarchitects and architects. The intention is to provide a general understanding of the circuits used in designing these arrays and their implied tradeoffs at the architectural level. We also want to bring attention to the architecture community on future issues facing memory arrays that can benefit from the collaboration of circuits and microarchitecture practitioners and researchers.

Steven Hsu: Steven K. Hsu has been with Intel Corporation for over 8 years, and is currently a Staff Research Engineer in the High-performance Circuits research group at Intel Corporation's Circuits Research Labs, Microprocessor Technology Labs, Hillsboro, Oregon. He received his BS, MS, and PhD degrees in computer engineering from Oregon State University in 1999, 2001 and 2006 respectively. His research interests include digital VLSI data-path, memory circuits, and micro-architecture. He has published over 20 conference/journal papers and holds 19 US patents.

Dinesh Somasekhar (S'95-M'98) received the B.S.E.E. degree from Maharaja Sayajirao University, Baroda, India, in 1989, the M.S.E.E. degree from the Indian Institute of Science, Bangalore, India, in 1991, and the Ph.D. degree from Purdue University, West Lafayette, IN, in 1999. From 1991 to 1994, he was an IC Design Engineer with Texas Instruments (TI), Bangalore, India, where he designed ASIC compiler memories and interface ICs. Since 1999, he has been with the Circuits Research Lab, Intel Corporation, Hillsboro. He holds 52 patents and has authored 36 papers. His interest areas are low voltage SRAMs, embedded DRAMs and stacked memories

Shih-Lien Lu: Shih-Lien Lu has been with Intel Corp for over 8 years, and is currently a Principal Research Scientist in the Microarchitecture research group. He received his BS in EECS from UC Berkeley, and MS and PhD both in CSE from UCLA. He worked on the MOSIS project at USC/ISI which provides research and education community VLSI fabrication services from 1984 to 1991. He joined the faculty of the ECE Dept. at Oregon State University in 1991. While at OSU, he received the College of Engineering Carter Award for outstanding and inspirational teaching in 1995 and the CoE/ECE Engelbrecht Young Faculty Award in 1996. His research interests include computer microarchitecture, circuits, and VLSI systems design.