This year's MICRO will feature two keynotes and a panel. The details on each of these is provided below.
Top five reasons why sequential programming models could be the best way to program many-core systems
Wen-mei Hwu, University of Illinois, Urbana-Champaign
The computer industry is at the stage of divergence in processor design. In the next few years, we will see heterogeneous multi-cores, homogeneous multi-cores, SPE-style accelerators, GPGPU style accelerators, ASIC-style accelerators, and FPGA-style accelerators. All these platforms will impose different machine-level programming models and constraints. It will be extremely tempting for vendors to provide explicitly parallel programming tools for these platforms. The higher the level of hardware parallelism, the stronger the temptation will be. In this talk, I will take a potentially unpopular position and argue that such approach will likely be counter productive in the long run. I will advocate a paradigm where programmers focus on algorithm-level parallelism and expressing the high-level assumptions/properties to the underlying programming tool chain. The compiler and related tools should be equipped with much more advanced bottom-up analysis capabilities and programmer assertions than what they have today in order to have a deep, comprehensive understanding of the real execution constraints of the input program. Such understanding is then used to drive automatic or interactive parallel code generation tools for the diverse set of machine-level programming models required by hardware platforms. I will give an incomplete survey of the field and present early indications that such model for parallel software development is both achievable and desirable.
Bio: Wen-mei W. Hwu has been a long-time participant of MICRO since 1985. He holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. His research interests are in the area of architecture, implementation, and software for high performance computer systems. He is the director of the IMPACT research group. For his contributions in research and teaching, he received the Eta Kappa Nu Outstanding Young Electrical Engineer Award, the Xerox Award for Faculty Research, the University Scholar Award of the University of Illinois, the Eta Kappa Nu Holmes MacDonald Outstanding Teaching Award, the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and ISCA Most Influential Paper Award. He is a fellow of IEEE and ACM. Hwu serves on the Executive Committee of the MARCO/DARPA C2S2 and GSRC Focus Research Centers. He leads the GSRC Concurrent Systems Theme with Kurt Keutzer. He also serves on the GELATO Strategy Council. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.
Attack of the Killer Game Machines
Sanjay J. Patel, University of Illinois, Urbana-Champaign
In early 2005, AGEIA introduced the notion of an accelerator card for physical simulation of video games. Since then, there has been a rush of activity from several major semiconductor vendors to jump onto the physics bandwagon. This is another example of how the semiconductor economy is responding to the "data scale" world, driven by the video games at its base, and extending into a revitalized workstation market. Physics is a good example of a data scale workload, and in this talk we'll examine the interesting challenges of designing chips for physics, and the economics that make it possible.
Bio: Sanjay J. Patel is an Associate Professor of Electrical and Computer Engineering and Willett Faculty Scholar at the University of Illinois at Urbana-Champaign, where he pursues his research interest in designing high-performance and error-tolerant architectures.
Since 2004, Sanjay has been the Chief Architect at AGEIA Technologies, overseeing the architecture and design of AGEIA's high-performance ASICs for accelerating physical simulation in video games.
He is the co-author (with Yale Patt of The University of Texas at Austin) of an introductory textbook for computer science and engineering students, titled "Introduction to Computing Systems: From Bits and Gates to C and Beyond", which is now available in its second edition from McGraw-Hill.
Patel earned his Bachelor (1990), Master of Science (1992) and PhD (1999) in Computer Science and Engineering from the University of Michigan, Ann Arbor.
Nanotechnology's Role in Shaping Future Architectures
Chair/Moderator: Alvin R. Lebeck, Duke University
Doug Burger, The University of Texas at Austin
Chris Dwyer, Duke University
Michael Niemier, Georgia Institute of Technology
Yale Patt, The University of Texas at Austin
Technology has always been a driving force for microarchitecture research. This year's MICRO panel will address issues surrounding the potential influence of nanotechnology (both emerging technologies and scaled CMOS) on future computer architectures. To address these issues from a broad perspective, the panel includes experts on nanotechnology along with experts on microarchitecture.