Adobe Systems Proceedings

37th International Symposium

on Microarchitecture

Table of Contents

Message from the General and Program Chairs................................................................... ix

Committees.......................................................................................................................................................................... x

Reviewers............................................................................................................................................................................. xii

Keynote 1

Chair: John Shen, Intel Corporation

Microarchitecture and Design Challenges for Gigascale Integration....................................................................................... 3

Shekhar Borkar, Intel Corporation

Session 1: Instruction Collapsing

Chair: Dean Tullsen, UCSD

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing

Pipeline Communication.................................................................................................................................................................. 7

P. G. Sassone and D. S. Wills

Dataflow Mini-graphs: Amplifying Superscalar Capacity and Bandwidth............................................................................ 18

A. Bracy, P. Prahlad, and A. Roth

Application-Specific Processing on a General-Purpose Core via Transparent

Instruction Set Customization...................................................................................................................................................... 30

N. Clark, M. Kudlur, H. Park, S. Mahlke, and K. Flautner

Session 2: Performance Evaluation

Chair: Pradip Bose, IBM

MicroLib: A Case for the Quantitative Comparison of Micro-architecture

Mechanisms.................................................................................................................................................................................... 43

D. Gracia Pérez, G. Mouchard, and O. Temam

Automatic Synthesis of High-Speed Processor Simulators..................................................................................................... 55

M. Burtscher and I. Ganusov

Thermal Modeling, Characterization and Management of On-Chip Networks..................................................................... 67

L. Shang, L.-S. Peh, A. Kumar, and N. K. Jha

Session 3: Trace Analysis

Chair: David Kaeli, Northeastern University

Pinpointing Representative Portions of Large Intel® Itanium® Programs

with Dynamic Instrumentation..................................................................................................................................................... 81

H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi

The Fuzzy Correlation between Code and Performance Predictability................................................................................... 93

M. Annavaram, R. Rakvic, M. Polito, J.-Y. Bouguet, R. Hankins, and B. Davies

Whole Execution Traces.............................................................................................................................................................. 105

X. Zhang and R. Gupta

Session 4: Control Flow

Chair: Scott Mahlke, University of Michigan

Wrong Path Events: Exploiting Unusual and Illegal Program Behavior

for Early Misprediction Detection and Recovery.................................................................................................................... 119

D. N. Armstrong, H. Kim, O. Mutlu, and Y. N. Patt

Control Flow Optimization via Dynamic Reconvergence Prediction.................................................................................... 129

J. D. Collins, D. M. Tullsen, and H. Wang

Keynote 2

Chair: Antonio González, UPC-Intel Labs

Single-Chip Multiprocessors: The Next Wave of Computer Architecture

Innovation..................................................................................................................................................................................... 143

Guri Sohi, University of Wisconsin-Madison

Session 5: Adaptive Microarchitectures

Chair: Babak Falsafi, CMU

A Case for Clumsy Packet Processors...................................................................................................................................... 147

A. Mallik and G. Memik

Dynamically Trading Frequency for Complexity in a GALS Microprocessor..................................................................... 157

S. Dropsho, G. Semeraro, D. H. Albonesi, G. Magklis, and M. L. Scott

Session 6: Multithreaded/Multicore Processors

Chair: Josep Torrellas, UIUC

Dynamically Controlled Resource Allocation in SMT Processors....................................................................................... 171

F. J. Cazorla, A. Ramirez, M. Valero, and E. Fernández

Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading

Hierarchy........................................................................................................................................................................................ 183

E. Tune, R. Kumar, D. M. Tullsen, and B. Calder

Conjoined-Core Chip Multiprocessing..................................................................................................................................... 195

R. Kumar, N. P. Jouppi, and D. M. Tullsen

Session 7: Security

Chair: Yale Patt, University of Texas at Austin

Hardware and Binary Modification Support for Code Pointer Protection

from Buffer Overflow.................................................................................................................................................................... 209

N. Tuck, B. Calder, and G. Varghese

Minos: Control Data Attack Prevention Orthogonal to Memory Model............................................................................. 221

J. R. Crandall and F. T. Chong

A Hardware-Software Platform for Intrusion Prevention....................................................................................................... 233

M. Drinić and D. Kirovski

RIFLE: An Architectural Framework for User-Centric Information-Flow Security............................................................. 243

N. Vachharajani, M. J. Bridges, J. Chang, R. Rangan, G. Ottoni, J. A. Blome,

G. A. Reis, M. Vachharajani, and D. I. August

Session 8: Reliability

Chair: Rajiv Gupta, University of Arizona

Efficient Resource Sharing in Concurrent Error Detecting Superscalar

Microarchitectures....................................................................................................................................................................... 257

J. C. Smolens, J. Kim, J. C. Hoe, and B. Falsafi

AccMon: Automatically Detecting Memory-Related Bugs via Program

Counter-Based Invariants........................................................................................................................................................... 269

P. Zhou, W. Liu, L. Fei, S. Lu, F. Qin, Y. Zhou, S. Midkiff, and J. Torrellas

Session 9: Code Generation and Optimization

Chair: Jim Dehnert, Transmeta

Optimal Superblock Scheduling Using Enumeration.............................................................................................................. 283

G. Shobaki and K. Wilken

Compiler Optimizations for Transaction Processing Workloads on Itanium®

Linux Systems............................................................................................................................................................................... 294

G. Hoflehner, K. Kirkegaard, R. Skinner, D. Lavery, Y. Lee, and W. Li

File Pressure.................................................................................................................................................................................. 304

O. Ergin, D. Balkan, K. Ghose, and D. Ponomarev

Session 10: Caches and Memory

Chair: Doug Burger, University of Texas at Austin

Managing Wire Delay in Large Chip-Multiprocessor Caches.............................................................................................. 319

B. M. Beckmann and D. A. Wood

Cache Refill/Access Decoupling for Vector Machines.......................................................................................................... 331

C. Batten, R. Krashinsky, S. Gerding, and K. Asanović

Adaptive History-Based Memory Schedulers......................................................................................................................... 343

I. Hur and C. Lin

Memory Controller Optimizations for Web Servers................................................................................................................ 355

S. Rixner

Author Index................................................................................................................................................................... 367

Message from the General and Program Chairs

We are very pleased to welcome you to the 37th International Symposium on Microarchitecture (MICRO-37). MICRO is the premier technical forum on microarchitecture and code generation techniques. This year we have the pleasure of holding MICRO in Portland, Oregon, an area long renowned for its natural attractions and scenic beauty—rivers, mountains, volcanoes, ocean beaches, and the Columbia gorge.

This year’s conference has a very attractive program that features several outstanding keynote speakers including Shekhar Borkar (Intel Fellow) and Guri Sohi (Professor, University of Wisconsin-Madison). The program also includes ten technical sessions with very interesting papers.

This year we received a very large number of high-quality submissions, which reflect the continuing vitality of the conference. The Program Committee had an intense and difficult task to select the final program from among these high-quality papers. Each submitted paper was reviewed by at least five people and the vast majority received six reviews, including four from the Program Committee members. On 7 August 2004, the Program Committee met in Sunnyvale and selected 29 papers for publication out of the 158 submissions. We would like to thank all the members of the Program Committee for their outstanding work on reviewing the papers and selecting the final program. We also thank the external reviewers. Their input has been very important for formulating the final program.

We would also like to thank our corporate sponsors, whose generosity helped us raise the bar on what this conference could accomplish: Intel, IBM, and Cadence. Thanks also go to IEEE Micro magazine for sponsoring the best-paper awards.

There are many other people who have contributed to this year’s outstanding conference. Special thanks go to Ramon Canal, who managed the conference Web site and assisted in many logistics for the reviewing process, and Ellen Colwell and Srikanth Srinivasan who helped in numerous aspects of the organization of the conference. We are also very grateful to Pepe González and Josep Lluis Larriba for their work as workshops chair and tutorial chair, respectively. Thanks also to the rest of the organizing committee: Pritpal Ahuja, David Brooks, Daniel Jiménez, Glenn Reinman, and Amir Roth. Finally, we gratefully acknowledge the advice and guidance provided by the members of the steering committee, and in particular its chair, Richard Belgard.

Bob Colwell and Kevin Skadron

General Chairs

Antonio González and John Shen

Program Chairs

Committees

Organizing Commitee

General Co-Chairs

Bob Colwell, R&E Colwell & Assoc

Kevin Skadron, University of Virginia

Program Co-Chairs

Antonio González, UPC/Intel Labs

John P. Shen, Intel

Conference Coordinator

Ellen Colwell, R&E Colwell & Assoc.

Local Arrangements Chair

Srikanth Srinivasan, Intel

Finance Chair

David Brooks, Harvard

Publications Chair

Daniel Jiménez, Rutgers

Publicity Chair

Glenn Reinman, UCLA

Student Advocate

Amir Roth, University of Pennsylvania

Tutorial Chair

Josep Lluis Larriba, UPC

Workshop Chair

José González, Intel

Web Co-Chairs

Pritpal S. Ahuja, Intel

Ramon Canal, UPC

Steering Committee

Richard Belgard, Consultant

Tom Conte, NC State

Kemal Ebcioglu, IBM

Wen-mei Hwu, UIUC

Scott Mahlke, University of Michigan

Bill Mangione-Smith, UCLA

Yale Patt, University of Texas at Austin

Andrew Wolfe, Consultant

Program Committee

Santosh Abraham, Sun

David Albonesi, Cornell

Bryan Black, Intel

Pradip Bose, IBM

Doug Burger, University of Texas at Austin

Brad Calder, UCSD

David Christie, AMD

Tom Conte, NC State

Jim Dehnert, Transmeta

Evelyn Duesterwald, IBM

Babak Falsafi, CMU

Dirk Grunwald, University of Colorado

Rajiv Gupta, University of Arizona

Wen-mei Hwu, UIUC

David Kaeli, Northeastern

Scott Mahlke, University of Michigan

Bill Mangione-Smith, UCLA

Margaret Martonosi, Princeton

Scott McFarling, Microsoft

Yale Patt, University of Texas at Austin

Steve Reinhardt, University of Michigan

Amir Roth, University of Pennsylvania

Jesús Sánchez, Intel/UPC
Mike Schlansker, HP

Per Stenstrom, Chalmers

Francisco Tirado, UCM

Josep Torrellas, UIUC

Dean Tullsen, UCSD

T. N. Vijaykumar, Purdue