Keynote Speak 1
Senior Technical Staff Member
IBM T.J. Watson Research Center
Yorktown Heights, NY
Microarchitecture and technology scaling have historically shared responsibility for the microprocessor’s phenomenal generation-over-generation performance improvement. The era marked by unrestrained proliferation of successively scaled, leakier devices to achieve incremental architectural transaction rate growth is coming to a close, however. Increased pipeline depth has caused non-linear latch density expansion; shorter FO4-equivalent cycles have made control logic substantially more complex. The resulting energy per operation, scaled-process-induced delay variation, logic corruption due to soft errors, and erosion in die area access latency have become real-world constraints. This talk will explore how features of past technologies have influenced high speed microarchitectures, and how the characteristics of proposed new devices and interconnects for lithographies beyond 90nm may shape future machine design. Given our industry’s power-restricted ability to continue scaling, and the approach of fundamental, quantum-mechanical precision boundaries, the role of microarchitecture in extending CMOS performance will be more important than ever.
Kerry Bernstein is a Senior Technical Staff Member at the IBM T.J. Watson Research Center, Yorktown Hts, NY. He is currently responsible for future product technology definition, performance and application. Mr. Bernstein received the B.S degree in electrical engineering degree from Washington University in St.Louis, and joined IBM in 1978. He holds 40 US Patents, and is a co-author of 3 college textbooks and multiple papers on high speed CMOS. His interests are in the areas of high performance circuit technology, delay variability, and CMOS radiation response. He is a senior member of IEEE, and is on the staff of “Research Update in Neuroscience” at Marine Biological Laboratories, Woods Hole, MA.