Reducing Register Ports for Higher Speed and Lower Energy
Authors:
Il Park, Michael D. Powell, and T. N. Vijaykumar
School of Electrical and Computer Engineering, Purdue University
Abstract:
The key issues for register file design in high-performance processors are
access time and energy. While previous work has focused on reducing the
number of registers, we propose to reduce the number of register ports
through two proposals, one for reads and the other for writes. For reads,
we propose bypass hint to reduce register port requirements by avoiding
unnecessary register file reads for cases where values are bypassed.
Current processors are unable to avoid these unnecessary reads due to
timing constraints. For writes, we use register file banking. Current
banking schemes assign different banks to instructions that are renamed
together, which does not necessarily avoid conflicts among instructions
that writeback together. We use decoupled rename, a technique which
separates dependence and physical tagging of register operands. Decoupled
rename allows us to perform physical register allocation just before
writeback, avoiding bank conflicts. Our results show that combining bypass
hint and write banking, our 1-cycle register file with 6 read ports, and
two 4-write-ported banks achieves a 9% processor energy-delay savings over
a system using a perfectly-pipelined, 2-cycle register file with 16 read
ports and 8 write ports.