Hierarchical Scheduling Windows
Authors:
Edward Brekelbaum, Jeff Rupley II, Chris Wilkerson, Bryan Black
(Microprocessor Research, Intel Labs)
Abstract:
Large scheduling windows are an effective mechanism for increasing
microprocessor performance through the extraction of instruction level
parallelism. Current techniques do not scale effectively for very large
windows, leading to slow wakeup and select logic as well as large
complicated bypass networks. This paper introduces a new instruction
scheduler implementation, referred to as Hierarchical Scheduling Windows or
HSW, which exploits latency tolerant instructions in order to reduce
implementation complexity. HSW yields a very large instruction window that
tolerates wakeup, select, and bypass latency, while extracting significant
far-flung ILP.
Results: It is shown that HSW loses <0.5% performance per additional cycle
of bypass/select/wakeup latency as compared to a monolithic window that
loses ~5% per additional cycle. Also, HSW achieves the performance of
traditional implementations with only 1/3 to 1/2 the number of entries in
the critical timing path.
Web Site:
No specific web site, general information available at: http://www.intel.com/research