Technology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned into components so that most of the communication is done locally. In this paper, we propose a novel register file organization for VLIW cores that combines clustering with a hierarchical register file organization. Functional units are organized in clusters with a local first level register file. The local register files are connected to a global second level register file, which provides access to memory. All inter-cluster communications are done through the second level register file. Compiler support is required to generate efficient code for such complex organization. This paper also proposes IMSC, a novel modulo scheduling technique that simultaneously performs instruction scheduling, cluster selection, inserts communication operations and performs register allocation and spill insertion for the proposed organization. The results show that although more cycles are required to execute applications, the execution time is reduced due to a shorter cycle time. In addition, the new organization also reduces power dissipation and die area when compared to monolithic register file organizations.