Select-Free Instruction Scheduling Logic

Mary D. Brown, The University of Texas at Austin
Jared Stark, Intel Corporation
Yale N. Patt, The University of Texas at Austin

Pipelining allows processors to exploit parallelism. Unfortunately, critical loops -- pieces of logic that must evaluate in a single cycle to meet IPC (Instructions Per Cycle) goals -- prevent deeper pipelining. In today's processors, one of these loops is the instruction scheduling (wakeup and select) logic. This paper describes a technique that pipelines this loop by breaking it into two smaller loops: a critical, single-cycle loop for wakeup; and a non-critical, potentially multi-cycle, loop for select. For the 12 SPECint2000 benchmarks, a machine with two-cycle select logic (i.e., three-cycle scheduling logic) using this technique has an average IPC 15% greater than a machine with three-cycle pipelined conventional scheduling logic, and an IPC within 3% of a machine of the same pipeline depth and one-cycle (ideal) scheduling logic. Since select accounts for more than half the scheduling latency, this technique could significantly increase clock frequency while having minimal impact on IPC.