Dynamic Binary Translation and Optimization
Wednesday, December 13, 2000
2:30 - 6:00 pm
Monterey Plaza Hotel
Dynamic binary translation has attracted a great deal of attention of late. Transmeta recently unveiled their Crusoe chip based on the idea of dynamically translating and optimizing x86 code for the underlying Crusoe processor (and requiring far less power than traditional x86 implementations). IBM's DAISY project was introduced in 1996 and uses similar techniques to emulate a PowerPC processor and achieve high instruction level parallelism on an underlying VLIW. One attraction of the dynamic binary translation approach is that hardware design complexity can be reduced by making a complex architecture a layer of software on a simpler one. Another attraction is the possibility of applying dynamic optimizations during the translation process, to improve performance. HP's Dynamo project emulates PA-RISC on PA-RISC, but can boost performance in the process. Java JIT compilers, such as LaTTe, use dynamic translation and optimization to move from Java Virtual Machine code to RISC code.
This tutorial will describe dynamic binary translation with particular emphasis on actual systems, and is aimed at those who may be interested in building or exploring such systems. Only a rudimentary knowledge of architecture, microarchitecture, and compilers is assumed.
Tutorial Timetable - Wednesday, December 13, 2000
Erik Altman is a research staff member at the T.J. Watson Research Center. Aside from being one of the originators of the DAISY project, his research interests include binary translation and optimization, compilers, architecture and microarchitecture. He received a PhD in Computer Science from McGill University.
Kemal Ebcioglu heads the DAISY project. He has been conducting research on compilers and architectures for instruction level parallelism topics (in particular VLIW) at the IBM T.J. Watson Research Center, since 1986. Dr. Ebcioglu has many technical publications and patents. He is the current ACM SIGMICRO chair, the steering committee chair for the Parallel Architectures and Compilation Techniques conference, and the vice president for North America for IFIP Working Group 10.3 (Concurrent Systems). He has served as general chair, program chair, program committee member and steering committee member for various conferences related to fine grain parallelism. He is an associate editor of the IEEE Transactions on Computers. His current research interests include Java, and dynamic binary-to-binary compilation toward achieving high ILP and hardware commonality across architectures. Ebcioglu received a Ph.D. in computer science from the State University of New York at Buffalo in 1986.