CALL FOR PAPERS 

MICRO-33

December 10-13, 2000

Monterey Plaza Hotel, Monterey, California

THE 33^rd ANNUAL IEEE/ACM INTERNATIONAL

SYMPOSIUM ON MICROARCHITECTURE  

with special emphasis on Instruction-Level Parallelism

Co-sponsored by IEEE TC-MARCH  and ACM SIGMICRO

 

General Chair Andrew Wolfe, S3 Inc [email protected]   Program Chair Mike Schlansker, HP Labs [email protected]   Workshop/Tutorial Chair Chris Newburn, Intel   Steering Committee Kemal Ebcioglu, IBM Tom Conte, NC State Richard Belgard, Consultant Wen-mei Hwu, Illinois Matt Farrens, UC Davis Yale Patt, Texas-Austin Ronny Ronen, Intel Jim Smith, Wisconsin   Program Committee Jim Bondi                    TI Pradip Bose                    IBM Bob Colwell                Intel Tom Conte                  NC State Henk Corporaal         Delft Jim Dehnert                SGI Kemal Ebcioglu         IBM Joel Emer                   Compaq Keith Farkas               Compaq Rajiv Gupta                 Arizona Wen-Mei Hwu             Illinois Lizy John                     Texas- Austin Richard Johnson       Transmeta Roy Dz-ching Ju         Intel Vinod Kathail              HP Labs Bill Mangione-Smith UCLA Hans Mulder               Intel Yale Patt                      Texas- Austin Ronny Ronen             Intel Andre Seznec             IRISA/INRIA Jim Smith                    Wisconsin Mike Smith                  Harvard Guri Sohi                     Wisconsin Lothar Thiele              ETH Zurich Carol Thompson       HP Gary Tyson                  Michigan Mateo Valero              UPC Barcelona Pen-Chung Yew  Minnesota

The 33rd International Symposium on Microarchitecture is the premiere forum for discussing new techniques to extract high levels of instruction-level parallelism via hardware and software. The goals of this symposium are to bring together researchers in fields related to microarchitecture and instruction-level parallelism, to encourage technical interaction, and to advance the state of the art of high-performance microarchitectures and fine-grain parallel processing.  Papers are solicited in fields including the following:   ·   ILP architectures and designs: superscalar, VLIW, multithreaded, ... ·   Compiler techniques for instruction-level parallelism ·   Hardware/software techniques for fine-grain parallel processing ·   Advanced software and hardware speculation schemes (branch/value prediction, etc.) ·   Hardware/compiler techniques for improving memory system performance ·   Object code translation ·   Hardware/software techniques for efficient systems on a single chip ·   Microarchitecture for embedded processing (imaging, graphics, low power, etc.) ·   Applications of ILP techniques to automated design   THE DEADLINE FOR SUBMISSIONS IS JUNE 19th, 2000.  There is an automatic, one week extension for late papers.  There will be no other extensions.  Submit one electronic copy of the paper in postscript or PDF format.  Please visit the website for paper format guidelines and submission instructions.  In order to guarantee the success of your electronic submissions please make sure that your postscript submission can be previewed via the ghostview tool.  Notification of acceptance will occur by September 1, 2000.   http://www.microarch.org/micro33